Crossing the gap between mathematics and physics This entire second season of The Art of FPGA Design will be about Digital Signal Processing. This is a vast subject one cannot cover in one book, let alone a few blog posts. It is a strange field ...
Hi, This is season 2 of the Art of FPGA Design blog. I plan to add a new post every Tuesday but depending on how long it will take me to create the content some posts could appear every other week. I have outlined below the first few posts I am ...
Stereopsis is the inference of depth by comparing two images from slightly different perspectives. There are a number of local and global algorithms used to obtain a real time stereo depth map. The computational requirements for stereo however are qu...
Hi! In this little guide I would like to show you how to create Minized project with Vitis 2020.1 support and PYNQ. If have problems with reading this blog visit hackster.io First thing first First thing we need is to clone Avnet...
Today, we take a look at how the prolific Adam Taylor got started and how you can too!If you have never heard of Adam…which rock have you been under!?Adam Taylor Founder and Principal Consultant, Adiuvo Engineering and Training is a rather humble eng...
Hi everyone! I wanted to let you all know that recently our Video Subject Matter Expert Jason Moss has recently finished the first cut at the ported VCU TRD, for 2020.1!He is currently working off of a branch from the official Avnet UltraZed-EV ...
Last year when Avnet released the Technical Training Courses for Ultra96, the courses were based on Xilinx 2018.3 tools, which did not include Xilinx Vitis. This 2018.3 Ultra96 TTC Series includes 8 total days of training across 6 different introduct...
Hello! Here goes my third tutorial on Minized and PYNQ using EMMC memory This project will prepare your Minized to work with PYNQ and give you some insight how to modify existing projects to suit your needs. Edit: added how to use Vitis HLS...
Hello! Here goes my second tutorial on Minized this time with PYNQ This is my first take on PYNQ and in future I will try to use different overlays and use FPGA based kernels for acceleration. Story A step by step take how to cre...
Hi! I have created this little tutorial how to prepare your Minized for some acceleration in Vitis 2019.2 Project is built based on Avnet BSP and shows whole platform creation process.Acceleration BSP is included in project, feel free to use you...
The idea of this little manual is to help FPGA beginners. Like everyone in the world we are not born knowing, and it is always useful to help so that the beginnings are not so difficult. I assume that if you are going to enter in the FPGA ...
Have you ever wished that your PetaLinux project didn't take so long to build? Have you ever wanted a way to make the build happen faster? Alas! There are simple steps to follow to accelerate your PetaLinux project build times. ...
Hi all, I know sometimes people have different levels of notifications on. So, I thought I would point out that we have updated the 2019.2 BSP images for PicoZed, MicroZed, and MiniZed (all flavors of each)!For more details, check out this...
This blog post is a long overdue continuation of the "Avnet HDL git HOWTO" blog post I wrote last year. Like the Avnet HDL github repository of build scripts, IP, etc. for building the Vivado projects that are the hardware foundation for custom...
Add System MonitorsUbuntu has the ability to manipulate the various desktop components. One such addition that is useful is to get mini-system monitors on the clutter bar.$ sudo apt-get install --yes gir1.2-gtop-2.0 gir1.2-networkmanager-1.0 gi...
Install File Editors and alternative File ExplorerUbuntu comes with gedit, diff (command line) and Nautilus. We have had feedback from many users that GEANY, MELD, and THUNAR are preferred.Who knows, maybe you will finally find a replacement fo...
Cleanup FavoritesUbuntu defaults to quite a selection of items on the favorites bar. These make sense if you are using this as a primary operating system. In the case of how we intend to use this, most of these do not make sense. It is su...
Make Terminal Easier to UseUpon completing the install of Ubuntu, terminal is setup with a default of 24 columns. As MOST paths and commands we typically work with in a Linux based Xilinx environment are rather long it can make sense to increase the ...
If you have not setup Vitis, you should first go back and visit my last blog where I talk about setting up the build environment.Learning Vitis: 1 Setting up a Virtual Machine Once you are caught up, if you have used SDSoC, or SDACCEL, you can s...
Disable Screen BlankingAssuming that you have seen the previous blogs and are using the Avnet recommended Ubuntu build environment, here is a tip that will increase your productivity!This is another tip that I found useful! If you have a tip yo...
Hi all, Welcome to a new series of blogs that I am putting together. If there is enough interest, I can continue this, so if you have suggestions and I can work it in, I will try to work through some blogs to answer your questions! Fo...
Within the Avnet 'Zed' Community, we spend a lot of time talking about SoC's with hard-core processors. The original ZedBoard started it all with a Zynq-7000 device with ARM A9. We've also done a lot with Zynq UltraScale+ family and ARM A53 (UltraZed...
