The next step in my Zynq and Pynq learning; get information from an FPGA design into the Linux part: a rotary decoder that can read the movement of a scroll wheel.
The original blog post for Spartan 6 and Xilinx ISE Webpack: Rotary Encoder...
Recently a, Ultra96-V2 user on the 96boards support forums asked the question "I was wondering if it was possible to connect to the UART directly via jumper leads? Anyone do this?" This is a good question, and it got me thinking. If you do...
Install Lattice DiamondLattice Diamond is developed on Red Hat and is not officially supported on Ubuntu; however with some persuasion, it can be made to work. Start by downloading the Lattice Diamond Linux package here: https://www.latticesemi...
The goal of this blog series is to master the Xilinx Zynq.
I'm using the PWM design of my previous posts, and now switch to the raw AXI memory map interface between ARM and FPGA.
In the previous post, I used AXI GPIO, the first step to memory map...
I posted a series of FPGA blogs. They focus on the toolchains and steps to get a working design.
A common theme in those articles is the VHDL source. Each time, it's a PWM generator.
A specific kind of PWM block: it can generate complementary output ...
The goal of this blog series is to master the Xilinx Zynq.
I'll try to build a PWM controller for a half bridge power design.
I've made a PWM with dead time design for the Xilinx Spartan 6 FPGA in 2017.I'm now learning to design for Zynq (...
Instructions on how to add the Pynq-Z2Pynq-Z2 board to Vivado.
This allows you to create projects and custom FPGA bit streams for it.
image source: customer action video after completing the instruction video of Cathal McCabe listed at the en...
When in Doubt, Check the Devicetree It recently came to our attention that the SATA interface was broken in Linux for the UltraZed-EV and UltraZed-EG. This is one of those "Wait! What? I know this worked before!" sorts of issues. Aft...
A bit about me
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KV260 SoM and carrier board
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PYNQ
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Using the KV260 with Viv...
Multichannel Symmetric FIRs In the last two posts we have considered the case when the FPGA clock frequency is faster than the FIR sample rate. The ratio between the system clock and the data sample rate is called the overclocking factor M. We h...
I previously wrote about Board Definitions in this blog:How to Leverage Board Presets to Accelerate Your Vivado Design That blog discussed creating your own Board Repo to add Board Definitions. Vivado has a built-in way to do this graphically, p...
This is an update to the popular Avnet HDL git HOWTO (Vivado 2020.1 and earlier) blog post. You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and Ult...
Hacking the Devicetree to Achieve the Linux QSPI Boot TrifectaThis is a tale of pain, grief, and redemption when working through strange Linux behavior and boot failures, and what happens when the devicetree doesn't match the underlying hardware.&nbs...
Multichannel and Overclocking FIRs - The Single Rate Symmetric Case In the last post I created an overclocked or semi-parallel implementation of a systolic, non-symmetric FIR, where each DSP48 in the chain implements M taps of the filter. ...
Interested in implemented AI at the edge with the Avnet platforms ? Check out my new designs for Vitis-AI 1.3, the latest edge AI solution for Xilinx based platforms. Vitis-AI 1.3 flow for Avnet Vitis platformsThis project provides detailed...
We've talked in this blog space and elsewhere about testing WiFi performance for the Ultra96-V2Ultra96-V2 board on a LAN using iperf3. It is a very handy and useful test, but it only tests local (WLAN) throughput. What about if you are de...
Multichannel and Overclocking FIRs - The Single Rate non-Symmetric Case We are looking now at the case of the single rate FIR filter where the sample rate is a sub-multiple of the FPGA clock rate. For example, let's say that the input ...
Taking advantage of coefficient symmetry in Polyphase FIRs We have seen in previous posts that when the FIR coefficients are symmetric, we can use a DSP48 feature called a pre-adder and reduce the number of multipliers required in half. Essenti...
It recently came to our attention at Avnet that PetaLinux QEMU boot was broken for our MicroZed SOMs, and possibly also broken for PicoZed, UltraZed, MiniZed, and Ultra96-V2. After spending some time to dive in and debug this problem we discove...
Polyphase Decimators The Polyphase Decimator FIR is the dual structure of the Polyphase Interpolator. The basic idea is that you can reduce the sample rate of a signal by a factor of M if you keep only one out of every M samples. This only works...
Polyphase Interpolators In the previous post we have looked at and important class of FIR filters, namely Polyphase architectures, which are extensively used for changing the sample rate of a signal by and integer factor, a process called interp...
