The Single Rate Half-Band FIR Decimator A decimating filter will reduce the sample rate of a signal, while preventing aliasing. Decimation by a factor of 2x is achieved by simply throwing out every second input sample. For this to work the input...
The Single Rate Half-Band FIR Interpolator In the previous post we looked at the single rate half-band FIR, a particular type of odd-symmetric FIR, where almost half of the filter coefficients are zero. Not computing multiplications with these z...
We are currently working on PetaLinux 2020.2 BSPs for the Avnet MicroZed, PicoZed, and UltraZed SOMs and MiniZed and Ultra96-V2 SBCs As part of these BSP updates we are also taking the time to make some much needed and overdue changes to the HDL...
As a follow up to the blog I posted on building the hardware design for the out of box image for the ON Semiconductor Dual Camera Mezzanine card, here are the instructions to complete the build with the Petalinux project. The original blog can be fou...
HI all, As I was working through updates for the 2020.2 release, I thought it might be useful to release some information about how much space you need to build.I worked through a chart of information and hope you can pick through the data and c...
Arty S7 Accelerometer-based pointer In a little bit more than a year ago I began experimenting with my first FPGA, the Digilent CMOD S7. FPGAs are quite flexible and can be used as programmable logic devices, but also as microcontrollers, since ...
Tic-Tac-Toe is one of the best known games in the world. A group of students port Tic Tac Toe to Digilent Arty A7 Field Programmable Gate Array (FPGA) platform. The game uses the classical Tic Tac Toe grid of 9 squares, running on a VGA monito...
I'm going to borrow heavily from my colleague Tom Curran and his excellent HDL howto blog (Avnet HDL git HOWTO (Vivado 2020.1 and earlier)). I highly recommend reading through that blog before continuing. I will modify it as needed to help you build ...
Xilinx Vitis 2020.2 Edge Acceleration on Hackster.ioDeveloping accelerated applications using the Xilinx Vitis tools may be straightforward, but the installation process can be daunting. This project aims to help new users clear the initial hurdle of...
The Single Rate Half-Band FIR We have started by looking at the most general version of an FIR filter. From a mathematical point of view, this is all that is needed. There are countless variations, like the symmetric versions, both odd and even,...
As you may already know, the Avnet Ultra96-V2Ultra96-V2 single board computer does not have a wired Ethernet port on the board. That means if we want higher Ethernet data throughput than the on-board WiFi can provide we need to go exploring for...
This project details how to build a stereo depth camera with AI capabilities on a ZYNQ MPSOC platform. This time we'll see how to use the Vitis Vison layer L1 libraries and PYNQ framework to implement a complete stereo depth pipeline.There a...
The Single Rate symmetric FIR, low latency transposed architecture The question we need to answer now is this - for those applications that require very low latency FIRs is there a way to avoid the increase in latency proportional to the filter ...
The Single Rate odd-symmetric FIR In the last post we have examined the even-symmetric FIR, a filter of order N=2*K. The main conclusion was that we only need K DSP48s to implement such a filter, and we came up with a basic building block that i...
The Single Rate even-symmetric FIR We have looked so far at the simplest and most generic FIR possible, the single rate non-symmetric FIR filter. But many FIR filter implementations have more particular structures and taking advantage of these c...
Hi all, I was working through some interesting designs on Vitis recently and a colleague of mine brought up a great question."What are the actual Vivado implementation settings for the different Vitis --optimize switches?" Not sur...
The Single Rate non-symmetric FIR, direct and transpose architectures As I mentioned earlier, the single rate non-symmetric FIR filter has two possible implementations, the direct and the transpose forms. We will now apply again the retiming and...
Register pushing and the pipeline cut It should be clear by now that a direct implementation of the DSP algorithm is not good enough. Every single individual computation block, the adders and the multipliers, will require pipeline registers and ...
Just to start off, not having worked within the design phase of FPGAs, let alone Xilinx, this workshop (or actually set of workshops) was like drinking from a fire hose. But like so many “new” things we try you get out of it what you put into i...
The basic building blocks on the FPGA implementation side The three main FPGA building blocks that are being used to implement the adders, multipliers and delays of DSP algorithms in hardware are completely different, the 6-input look up table, ...
Hi all, In preparation for my next Vitis blog, "Learning Vitis 5 Getting started with a custom Vitis Platform" we had been wrapping our heads around Vitis and what it means for you!Taking feedback from the field and trying to consider ...
A lot of the recent discussion of FPGAs on E14 recently has been focused on huge great SOC type parts running Linux - this project is at completely the other end of the scale. I'm looking at using Gowin's FPGAs in a couple of new d...
The basic building blocks on the DSP algorithm side The DSP algorithms that need to be implemented are relatively simple, mathematically speaking. They consist of three basic operations, additions, multiplications and vector or matrix indexing. ...
You have an Ultra96-V2 board, but want more data throughput than the on-board WiFi can provide. What do you do? A USB-to-Ethernet adapter (USB 3.0 GbE adapterUSB 3.0 GbE adapter) is inexpensive and provides excellent throughput, but requi...
