I've been studying Error Correcting Code (ECC) capability lately, specifically as it relates to Xilinx.
What is ECC?
Definition: Error correction code (ECC) checks read or transmitted data for errors and corrects them as soon as they are found....
I'm going to try and run an i2c design in VHDL fabric. For self-training.The target device is the Rohm BH1790 optical heart rate sensor. It's a device where the i2c protocol is straightforward but strict. A good candidate for training - a RTL state m...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial describes how to perform final installation and execution of the cust...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial describes how to combine all the parts that we built in the previous ...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial describes how to build the petalinux project for the Kria KV260 Visio...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial will re-compile the sixteen (16) supported models used by the smart_m...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial describes how to adapt and build the smart_model_select example for o...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial describes how to create the Vitis Platform for our custom Kria App.
B...
When Xilinx launched Kria , they also provided a method for quickly deploying apps. This project tutorial takes a deep dive into how to create a custom Kria app.
Introduction
On April 20, 2021, Xilinx announced Kria , their newest p...
This blog is part of a series of blogs which describe the development steps for an in-depth project tutorial.
http://avnet.me/kv260-vvas-sms-2021-1-blog
This part of the tutorial provides a description of the Xilinx repositories that will be used.
...
Introduction
I'm participating in the Hackster.io Edge Computing with Xilinx Kria KV260 Vision AI Starter Kit Challenge. My application The Kitchen ML Lifeguard was selected for the free hardware.
I will be publishing on this channel my ex...
Zynq controllers can run Linux. Xilinx uses Vitis - an Eclipse derivate - as the development platform for the ARM part of the Zynq.We'll use it to build - and debug! - a native Linux program.
Vitis knows how to program for the ARM proc...
The goal of this post is turn a fixed VHDL design into a configurable one. Change a fixed RAM IP into RAM that can be sized, without changing source or logic.
I use michaelkellett's VHDL RAM Memory design before: use RAM...
The Zynq family has an on-board 12 bit ADC, in the FPGA part of the silicon. They call it the XADC.It can sample internal rails and temperatures. There's also the possibility to use external inputs.In this series of 2 blogs, I'm trying to sample...
This is a supporting post for Part 2: Add the Accelerated IP to a Vivado design.I'm untangling the different data streams.There are 3 types of data exchanged between the FPGA and ARM parts of the Zynq:
"Business Data": the inputs and outputs to...
I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.
Use the Accelerated function in Software
In part 1, we made the hardwa...
I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience.
Register the IP and Use it in Vivado
In part 1, we made the hardware a...
PYNQ now supports Vivado and Vitis HLS version 2020.2 (since PYNQ 2.7).Time to re-check the hardware accelerator mechanisms, with DMA. This workflow has now stabilised.
Hardware Acceleration is the technique to implement program logic insi...
Yesterday, the PYNQ community released version 2.7 of the the PYNQ OS.SD Card images are available for download.
What's new:
Vivado, Vitis HLS version 2020.2
Python 3.8
Additional boards supported
Composable overlay pipeline
Petalinux 2020.2, U...
I was asked by my colleague ctammann to provide a design for the Kria KV260 Vision Starter Kit that would be a power hog for some power testing. Although all of the Kria apps seems to be using a B3136 DPU, I did remember that Xilinx genera...
Introduction
Quick little project to make an egg timer using the MAX II board that I bought over the summer.
Initially, I'll just have it counting down from three minutes. If I feel suitably inspired later, I
might extend it to allow setting t...
Avnet is working on Vitis 2021.1 platforms for several of their hardware platforms.Thanks to this work, I was able to port Vitis-AI 1.4 on the following platforms:Ultra96-V2 Development BoardUltraZed-EV SOM (7EV) + FMC Carrier CardUltraZed-EG SOM (3E...
Recent Advances in Vivado VHDL-2008 Support
Previous posts in this blog were made in the 2018-2019 period. Some of the issues presented were an attempt to work around VHDL-2008 support limitations in Vivado at that point in time. Since then, s...
Our team at Avnet is working on a new design now. As we go through the various review stages, I was reminded of something that every engineer developing a PCB with Xilinx should know. Tip #1 -- Use Xilinx Documentation NavigatorOf course, every ...
