Build a big multiplexer by reusing small multiplexers.
FPGA designs are (re)usable as components. In this post I'm showing that you can make a 4-input multiplexer by combining several 2-input multiplexers.
A 2-input multiplexer is a simple digita...
You can interrupt the Zynq ARM side with a signal coming out of the FPGA part of the chip. In this post, I test this.
The FPGA part has a few blocks that will generate interrupts. In a Jupyter notebook, I'll try to show that they are detected by the ...
IntroductionThis blog post provides details on how to build and execute the new 2020.2 design for the Ultra96-V2 development board with Dual-Camera Mezzanine. {gallery} Ultra96-V2 Dual Camera PhotosUltra96-V2 with Dual Camera MezzanineUltr...
Hello! Looking for a new Xilinx SBC to play with or the best Xilinx Zynq or Zynq UltraScale+ SOM to use in your product? Can't decide what Avnet SOM or SBC is the best fit for your application? Avnet has just published a new Xili...
When you're working on a Vivado Block design, you can add IP.
There are 100s of options available. But you will not find a NOT gate, AND gate, ...
They are there though, available under the cryptical name Utility Vector Logic and Utility Reduced Logi...
Introduction: Back then in February when I roadtested the USB104-A7, I had learned to create block designs using MicroBlaze. I found it very interesting but the available online resources were limited, the tutorials were based on the older versions o...
Read this for info only. The project done at the time didn't work. I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.It works, and can easily be repeated, with Vitis HLS...
Read this for info only. The project done at the time didn't work.
I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.
It works, and can easily be repeated, with Vi...
Life hack to automate the creation of a project in Vivado.
www.youtube.com/watch
video source: real time capture of script execution on my laptop
Many projects have repeatable steps at the setup stage. This script helps to automate this...
The main target for Zynq family FPGAs is: compute systems with hardware acceleration.
It's architecture focuses on being able to stream data efficiently between ARM and FPGA submodules.
The FPGA can then perform manipulations in hardware that tak...
shabaz made a Software Defined Radio (SDR) Experiment Board. One of the components is a digital quadrature oscillator.
It's a circuit with 4 PWM outputs that are each 90° shifted.
In Shabaz' blog, the oscillator is made with flip-flops, and cont...
Store 1024 12 bit values in a VHDL RAM design, and automatically test it.
This post uses the VHDL RAM design of Michael Kellett on a Zynq. You can store data and read it back.
The design was done out of curiousity. To see how and when Block RA...
Every FPGA and Programmable Logic SoC development board has the ability to plug in add-on boards to expand the functionality of the basic board. When you are deciding on which board to use for your own learning or proof-of-concept, it's important to ...
I've been following the discussions about the VIDOR4000 in the FPGA group. There was a giveaway associated with the Webinar but of course there will be sonme disapointed non-winners. If you want to get into playing with FPGAs one of the chea...
Have you heard about Xilinx’s latest release in the 16nm line, the ZU1/2/3 InFO package? This package uses 60% less area and is roughly 70% thinner than standard Zynq UltraScale+ chip. InFO (for those that don’t know) stands for Integrated Fan-Out. T...
Introduction Now a little project: a servo interface. This will give me a chance to experiment with some very simple communication between the microcontroller and the FPGA on my VIDOR 4000 board. I'm going to have 8 servo channels...
Without connecting anything else to the VIDOR, the only clock we're given to work with is one that comes from the SAM microcontroller. Here it is on the VIDOR schematic, output from the SAM part and going into one of the dedicated clock inputs.&n...
Introduction In this blog Add Pynq-Z2 board to Vivado Jan refers to a Johnson counter. I struggled to remember what a Johnson counter actually was, but, for some reason, the number 4017 came to mind. Sure enough, the CD4017 CMOS logic device tur...
The next step in my Zynq and Pynq learning; get information from an FPGA design into the Linux part: a rotary decoder that can read the movement of a scroll wheel.
The original blog post for Spartan 6 and Xilinx ISE Webpack: Rotary Encoder...
Recently a, Ultra96-V2 user on the 96boards support forums asked the question "I was wondering if it was possible to connect to the UART directly via jumper leads? Anyone do this?" This is a good question, and it got me thinking. If you do...
Install Lattice DiamondLattice Diamond is developed on Red Hat and is not officially supported on Ubuntu; however with some persuasion, it can be made to work. Start by downloading the Lattice Diamond Linux package here: https://www.latticesemi...
