Blog

Vitis-AI 1.4 Flow for Avnet Vitis platforms

albertabeef

Avnet is working on Vitis 2021.1 platforms for several of their hardware platforms.Thanks to this work, I was able to port Vitis-AI 1.4 on the following platforms:Ultra96-V2 Development BoardUltraZed-EV SOM (7EV) + FMC Carrier CardUltraZed-EG SOM (3E...
- 20 Oct 2021
The Art of FPGA Design - Post 37

fpgaguru

Recent Advances in Vivado VHDL-2008 Support Previous posts in this blog were made in the 2018-2019 period. Some of the issues presented were an attempt to work around VHDL-2008 support limitations in Vivado at that point in time. Since then, s...
- 3 Oct 2021
3 Tips You Should Know Before Developing a Xilinx PCB

bhfletcher

Our team at Avnet is working on a new design now. As we go through the various review stages, I was reminded of something that every engineer developing a PCB with Xilinx should know. Tip #1 -- Use Xilinx Documentation NavigatorOf course, every ...
- 29 Sep 2021
Learning Xilinx Zynq: reuse and combine components to build a multiplexer

Jan Cumps

Build a big multiplexer by reusing small multiplexers. FPGA designs are (re)usable as components. In this post I'm showing that you can make a 4-input multiplexer by combining several 2-input multiplexers. A 2-input multiplexer is a simple digita...
- 14 Sep 2021
Learning Xilinx Zynq: Interrupt ARM from FPGA fabric

Jan Cumps

You can interrupt the Zynq ARM side with a signal coming out of the FPGA part of the chip. In this post, I test this. The FPGA part has a few blocks that will generate interrupts. In a Jupyter notebook, I'll try to show that they are detected by the ...
- 5 Sep 2021
Ultra96-V2 Dual Camera Design for 2020.2

albertabeef

IntroductionThis blog post provides details on how to build and execute the new 2020.2 design for the Ultra96-V2 development board with Dual-Camera Mezzanine. {gallery} Ultra96-V2 Dual Camera PhotosUltra96-V2 with Dual Camera MezzanineUltr...
- 3 Sep 2021
Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency

Jan Cumps

This post is a follow up on a previous article to generate a quadrature clock for shabaz 's Software Defined Radio (SDR) Experiment Board. It's a circuit with 4 PWM outputs that are each 90° shifted. I'm adding programmable frequency control. Wit...
- 31 Aug 2021
Summer of FPGA, Workshop 4: Elaborating on the workshop design

Andrew J

IntroductionWorkshop 4 of the Summer of FPGA series for the Ultra96-V2 board went through a design for using the Mezzanine Click board. It was covered 'at pace' and this blog is my jottings on the steps taken, specifically elaborating on some o...
- 27 Aug 2021
Summer of FPGA, Workshop 4: Elaborating on creating custom IP

Andrew J

IntroductionWorkshop 4 of the Summer of FPGA series for the Ultra96-V2 board went through a design for using the Mezzanine Click board. It was covered 'at pace' and this blog is my jottings on the steps taken, specifically elaborating o...
- 27 Aug 2021
New! Avnet Boards Xilinx Solutions Guide

narrucmot

Hello! Looking for a new Xilinx SBC to play with or the best Xilinx Zynq or Zynq UltraScale+ SOM to use in your product? Can't decide what Avnet SOM or SBC is the best fit for your application? Avnet has just published a new Xili...
- 26 Aug 2021
Learning Xilinx Zynq: Logic Gates in Vivado

Jan Cumps

When you're working on a Vivado Block design, you can add IP. There are 100s of options available. But you will not find a NOT gate, AND gate, ... They are there though, available under the cryptical name Utility Vector Logic and Utility Reduced Logi...
- 18 Aug 2021
Summer of FPGAs - Building an Embedded System on FPGA

yesha98

Introduction: Back then in February when I roadtested the USB104-A7, I had learned to create block designs using MicroBlaze. I found it very interesting but the available online resources were limited, the tutorials were based on the older versions o...
- 16 Aug 2021
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design

Jan Cumps

Read this for info only. The project done at the time didn't work. I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.It works, and can easily be repeated, with Vitis HLS...
- 16 Aug 2021
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS

Jan Cumps

Read this for info only. The project done at the time didn't work. I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example. It works, and can easily be repeated, with Vi...
- 15 Aug 2021
Automate Repeatable Steps in Vivado

Jan Cumps

Life hack to automate the creation of a project in Vivado. www.youtube.com/watch video source: real time capture of script execution on my laptop Many projects have repeatable steps at the setup stage. This script helps to automate this...
- 12 Aug 2021
Learning Xilinx Zynq: Hardware Accelerated Software

Jan Cumps

The main target for Zynq family FPGAs is: compute systems with hardware acceleration. It's architecture focuses on being able to stream data efficiently between ARM and FPGA submodules. The FPGA can then perform manipulations in hardware that tak...
- 8 Aug 2021
Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

Jan Cumps

shabaz made a Software Defined Radio (SDR) Experiment Board. One of the components is a digital quadrature oscillator. It's a circuit with 4 PWM outputs that are each 90° shifted. In Shabaz' blog, the oscillator is made with flip-flops, and cont...
- 4 Aug 2021
Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ

Jan Cumps

Store 1024 12 bit values in a VHDL RAM design, and automatically test it. This post uses the VHDL RAM design of Michael Kellett on a Zynq. You can store data and read it back. The design was done out of curiousity. To see how and when Block RA...
- 2 Aug 2021
6 Ways to Expand the Functionality of your Xilinx FPGA Board

bhfletcher

Every FPGA and Programmable Logic SoC development board has the ability to plug in add-on boards to expand the functionality of the basic board. When you are deciding on which board to use for your own learning or proof-of-concept, it's important to ...
- 1 Aug 2021
Cheap Cyclone 10

michaelkellett

I've been following the discussions about the VIDOR4000 in the FPGA group. There was a giveaway associated with the Webinar but of course there will be sonme disapointed non-winners. If you want to get into playing with FPGAs one of the chea...
- 31 Jul 2021
What Do You Think About Xilinx’s 16nm ZU1/2/3 InFO Package?

jafoste4

Have you heard about Xilinx’s latest release in the 16nm line, the ZU1/2/3 InFO package? This package uses 60% less area and is roughly 70% thinner than standard Zynq UltraScale+ chip. InFO (for those that don’t know) stands for Integrated Fan-Out. T...
- 30 Jul 2021
VIDOR 4000: Servo Interface

jc2048

Introduction Now a little project: a servo interface. This will give me a chance to experiment with some very simple communication between the microcontroller and the FPGA on my VIDOR 4000 board. I'm going to have 8 servo channels...
- 29 Jul 2021
VIDOR 4000: Clock Jitter

jc2048

Without connecting anything else to the VIDOR, the only clock we're given to work with is one that comes from the SAM microcontroller. Here it is on the VIDOR schematic, output from the SAM part and going into one of the dedicated clock inputs.&n...
- 12 Jul 2021
VIDOR 4000: Johnson Counter

jc2048

Introduction In this blog Add Pynq-Z2 board to Vivado Jan refers to a Johnson counter. I struggled to remember what a Johnson counter actually was, but, for some reason, the number 4017 came to mind. Sure enough, the CD4017 CMOS logic device tur...
- 10 Jul 2021
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control

Jan Cumps

DIY Test Instrumentation Submit an Entry Submit an Entry Monthly Themes | Monthly Poll | Back to homepage This DIY instrument is a PWM generator with dead band support. It...
- 9 Jul 2021