One of the primary goals of element14's Summer of FPGAs is to put a focus on FPGA technology and provide our members interesting content and activities to expand their knowledge of programmable logic devices. To this end, I want to point to an element14 expert blogger on the subject of FPGAs, fpgaguru. His name is Catalin Baetoniu and he has an ongoing series he calls The Art of FPGA Design Season 2 - Digital Signal Processing, from Algorithm to FPGA Bitstream. In the first season of The Art of FPGA Design, he wrote 36 blogs. In the second season, he has written 18 blogs to date. It's a significant body of work that will teach you and more. I should add that Catalin is a Xilinx employee, but from what I read of his blog series, I would not say what he writes about is intended to be Xilinx-product-focused; rather he talks about the technology. This is truly a tech blog series.
I'm writing this to introduce you to his second season (links posted below), which focuses Digital Signal Processing using FPGAs. While it is not written on a beginner's level, I found it very readable and informative. It inspired me to read and learn more about both FPGAs and DSP. In his own words, Catalin describes the second season as an opportunity to explain "how to cross the gap between a DSP algorithm and its efficient implementation in an FPGA, something that is rarely explained or even discussed." He will also answer the important question: "How do you go from an algorithm specification, which is essentially mathematics to an actual hardware implementation where you have to live within the constraints imposed on you by the laws of physics."
Without further ado, let me stand aside and let you start reading a most interesting set of blogs:
The Art of FPGA Design Season 2 Post 1 - Crossing the gap between mathematics and physics
The Art of FPGA Design Season 2 Post 2 - The basic building blocks on the DSP algorithm side
The Art of FPGA Design Season 2 Post 3 - The basic building blocks on the FPGA implementation side
The Art of FPGA Design Season 2 Post 4 - Register pushing and the pipeline cut
The Art of FPGA Design Season 2 Post 5 - The Single Rate non-symmetric FIR, direct and transpose architectures
The Art of FPGA Design Season 2 Post 6 - The Single Rate even-symmetric FIR
The Art of FPGA Design Season 2 Post 7 - The Single Rate odd-symmetric FIR
The Art of FPGA Design Season 2 Post 8 - The Single Rate symmetric FIR, low latency transposed architecture
The Art of FPGA Design Season 2 Post 9 - The Single Rate Half-Band FIR
The Art of FPGA Design Season 2 Post 10 - The Single Rate Half-Band FIR Interpolator
The Art of FPGA Design Season 2 Post 11 - The Single Rate Half-Band FIR Decimator
The Art of FPGA Design Season 2 Post 12 - Polyphase FIRs
The Art of FPGA Design Season 2 Post 13 - Polyphase Interpolators
The Art of FPGA Design Season 2 Post 14 - Polyphase Decimators
The Art of FPGA Design Season 2 Post 15 - Taking advantage of coefficient symmetry in Polyphase FIRs
The Art of FPGA Design Season 2 Post 16 - Multichannel and Overclocking FIRs - The Single Rate Non-Symmetric Case
The Art of FPGA Design Season 2 Post 17 - Multichannel and Overclocking FIRs - The Single Rate Symmetric Case
The Art of FPGA Design Season 2 Post 18 - Multichannel Symmetric FIRs
Previously on the Art of FPGA Design:
The Art of FPGA Design Season 1 - A 36-post blog on advanced VHDL design topics for Xilinx FPGAs
If you had a opportunity to read these blogs, what did you find most informative about them? (Please Leave a Comment)
