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FPGA requires membership for participation - click to join
  • All tags
  • ultrazed-ev
  • amd
  • avnet
  • designed by avnet
  • hailo
  • microzed
  • minized
  • opsero
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  • zynq-ultrascale+
  • RPI Camera Fun with Zynq-UltraScale+ : LIBCAMERA

    RPI Camera Fun with Zynq-UltraScale+ : LIBCAMERA

    albertabeef
    albertabeef
    Introduction This project is part 4 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fun with…
    • 2 months ago
    • FPGA
    • Blog
  • RPI Camera Fun with Zynq-UltraScale+ : White Balance

    RPI Camera Fun with Zynq-UltraScale+ : White Balance

    albertabeef
    albertabeef
    Introduction This project is part 3 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fun with…
    • 2 months ago
    • FPGA
    • Blog
  • RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V3, HQ, AI

    RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V3, HQ, AI

    albertabeef
    albertabeef
    Introduction This project is part 2 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fun with…
    • 3 months ago
    • FPGA
    • Blog
  • RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2

    RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2

    albertabeef
    albertabeef
    Introduction This project is part 1 of a N part series of projects, where we will explore how to integrate Raspberry Pi cameras on Zynq-UltraScale+ boards. Part 1 : RPI Camera Fun with Zynq-UltraScale+ : RPI Cam V2 Part 2 : RPI Camera Fun with…
    • 3 months ago
    • FPGA
    • Blog
  • Tria Vitis Platforms — Adding support for ROS2

    Tria Vitis Platforms — Adding support for ROS2

    albertabeef
    albertabeef
    Introduction This project is part 5 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
    • 4 months ago
    • FPGA
    • Blog
  • Tria Vitis Platforms — Adding support for Hailo-8

    Tria Vitis Platforms — Adding support for Hailo-8

    albertabeef
    albertabeef
    Introduction This project is part 4 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
    • 4 months ago
    • FPGA
    • Blog
  • Tria Vitis Platforms — Adding support for Vitis-AI 3.5

    Tria Vitis Platforms — Adding support for Vitis-AI 3.5

    albertabeef
    albertabeef
    Introduction This project is part 3 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
    • 5 months ago
    • FPGA
    • Blog
  • Tria Vitis Platforms -   Creating a Common Platform

    Tria Vitis Platforms -   Creating a Common Platform

    albertabeef
    albertabeef
    Introduction This project is part 2 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
    • 5 months ago
    • FPGA
    • Blog
  • Tria Vitis Platforms — Building the Foundational Designs

    Tria Vitis Platforms — Building the Foundational Designs

    albertabeef
    albertabeef
    Introduction This project is part 1 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
    • 5 months ago
    • FPGA
    • Blog

  • Vitis-AI 2.0 Flow for Avnet Vitis platforms

    albertabeef
    albertabeef
    Avnet is working on Vitis 2021.2 platforms for several of their hardware platforms. Thanks to this work, I was able to port Vitis-AI 2.0 on the following platforms: Ultra96-V2 Development Board UltraZed-EV SOM (7EV) + FMC Carrier Card UltraZed…
    • over 3 years ago
    • FPGA
    • Blog

  • New NVMe (PCIe) PetaLinux BSP for the UltraZed-EV

    narrucmot
    narrucmot
    Hi Everyone! New with the release of BSPs for PetaLinux 2021.1 is a BSP that adds NVMe SSD capability to the UltraZed-EV ! What is NVMe? It is the industry standard for solid state drives (SSDs). The NVMe specification was designed specifically to…
    • over 3 years ago
    • FPGA
    • Blog

  • New! Avnet Boards Xilinx Solutions Guide

    narrucmot
    narrucmot
    Hello! Looking for a new Xilinx SBC to play with or the best Xilinx Zynq or Zynq UltraScale+ SOM to use in your product? Can't decide what Avnet SOM or SBC is the best fit for your application? Avnet has just published a new Xilinx Solutions Guide: Avnet…
    • over 3 years ago
    • FPGA
    • Blog

  • Fixing SATA for the UltraZeds

    narrucmot
    narrucmot
    When in Doubt, Check the Devicetree It recently came to our attention that the SATA interface was broken in Linux for the UltraZed-EV and UltraZed-EG. This is one of those "Wait! What? I know this worked before!" sorts of issues. After doing some sleuthing…
    • over 3 years ago
    • FPGA
    • Blog

  • Xilinx BoardStore to Automate Vivado Board Definitions for Avnet Boards

    bhfletcher
    bhfletcher
    I previously wrote about Board Definitions in this blog: How to Leverage Board Presets to Accelerate Your Vivado Design That blog discussed creating your own Board Repo to add Board Definitions. Vivado has a built-in way to do this graphically, pulling…
    • over 3 years ago
    • FPGA
    • Blog

  • Using Avnet Build Scripts to Build a PetaLinux BSP (2020.1 and later)

    narrucmot
    narrucmot
    This is an update to the popular Using Avnet Build Scripts to Build a PetaLinux BSP (2019.2 and earlier) blog post. Like the Avnet HDL github repository of build scripts, IP, etc. for building the Vivado projects that are the hardware foundation for customers…
    • over 3 years ago
    • FPGA
    • Blog

  • Avnet HDL git HOWTO (Vivado 2020.2 and later)

    narrucmot
    narrucmot
    This is an update to the popular Avnet HDL git HOWTO (Vivado 2020.1 and earlier) blog post. You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and UltraZed…
    • over 3 years ago
    • FPGA
    • Blog

  • Bring your AI projects to the Edge with Xilinx Vitis-AI and win $500 !

    albertabeef
    albertabeef
    Interested in implemented AI at the edge with the Avnet platforms ? Check out my new designs for Vitis-AI 1.3, the latest edge AI solution for Xilinx based platforms. Vitis-AI 1.3 flow for Avnet Vitis platforms This project provides detailed instructions…
    • over 4 years ago
    • FPGA
    • Blog

  • Big Changes Coming for Avnet git Repos for Zeds, UltraZeds, and Ultra96-V2

    narrucmot
    narrucmot
    We are currently working on PetaLinux 2020.2 BSPs for the Avnet MicroZed, PicoZed, and UltraZed SOMs and MiniZed and Ultra96-V2 SBCs As part of these BSP updates we are also taking the time to make some much needed and overdue changes to the HDL, PetaLinux…
    • over 4 years ago
    • FPGA
    • Blog

  • I know big, but how big? A look at hard drive space with Avnet SOMs

    drozwood90
    drozwood90
    HI all, As I was working through updates for the 2020.2 release, I thought it might be useful to release some information about how much space you need to build. I worked through a chart of information and hope you can pick through the data and create…
    • over 4 years ago
    • FPGA
    • Blog

  • 2020.1 Vitis Repo Changes!

    drozwood90
    drozwood90
    Hi all, In preparation for my next Vitis blog, "Learning Vitis 5 Getting started with a custom Vitis Platform" we had been wrapping our heads around Vitis and what it means for you! Taking feedback from the field and trying to consider what an end user…
    • over 4 years ago
    • FPGA
    • Blog

  • UltraZed-EV VCU (Video Codec Unit) Design 2020.1

    drozwood90
    drozwood90
    Hi everyone! I wanted to let you all know that recently our Video Subject Matter Expert Jason Moss has recently finished the first cut at the ported VCU TRD, for 2020.1! He is currently working off of a branch from the official Avnet UltraZed-EV EVCC…
    • over 4 years ago
    • FPGA
    • Blog

  • Accelerating PetaLinux BSP Build Time

    narrucmot
    narrucmot
    Have you ever wished that your PetaLinux project didn't take so long to build? Have you ever wanted a way to make the build happen faster? Alas! There are simple steps to follow to accelerate your PetaLinux project build times. As much as a 50% reduction…
    • over 4 years ago
    • FPGA
    • Blog

  • Using Avnet Build Scripts to Build a PetaLinux BSP (2019.2 and earlier)

    narrucmot
    narrucmot
    This blog post is a long overdue continuation of the " Avnet HDL git HOWTO " blog post I wrote last year. Like the Avnet HDL github repository of build scripts, IP, etc. for building the Vivado projects that are the hardware foundation for customers to…
    • over 4 years ago
    • FPGA
    • Blog

  • Learning Vitis: 4 How to TEST an Example Application

    drozwood90
    drozwood90
    Having previously gone through my previous blogs, you now have an output and want to test it! Learning Vitis: 1 Setting up a Virtual Machine Learning Vitis: 2 How to Download and "install" a pre-built platform Learning Vitis: 3 How to build an Example…
    • over 4 years ago
    • FPGA
    • Blog

  • Learning Vitis: 3 How to build an Example Application

    drozwood90
    drozwood90
    If you have not already checked out the previous blogs do so now! Learning Vitis: 1 Setting up a Virtual Machine Learning Vitis: 2 How to Download and "install" a pre-built platform Once you have completed those, you are in a position to use the platforms…
    • over 4 years ago
    • FPGA
    • Blog
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