• Booting ZUB1CG with AES-ACC-DPEMMC-G

    Project Purpose: The primary goal of this project is to explore and showcase the capabilities of the AES-ACC-DPEMMC-G module. This includes demonstrating its functionality, explaining its operation, and deploying it in practical scenarios. Although…

  • New! Use Linux ConnMan to Configure Ultra96-V2 WiFi

    Hi Everyone! New with the PetaLinux 2021.1 BSP for the Ultra96-V2 is the addition of the ConnMan connection manager software application to configure and maintain the WiFi connection. What is ConnMan? It is a Linux software daemon (connmand) for managing…

  • New NVMe (PCIe) PetaLinux BSP for the UltraZed-EV

    Hi Everyone! New with the release of BSPs for PetaLinux 2021.1 is a BSP that adds NVMe SSD capability to the UltraZed-EV ! What is NVMe? It is the industry standard for solid state drives (SSDs). The NVMe specification was designed specifically to…

  • How do you use PetaLinux & Yocto?

    Calling all Xilinx SoC users... You may know that Xilinx offers a Linux build environment called PetaLinux. It is a "productivity layer" on top of a Yocto/BitBake backend. There seems to be an obvious progression, where you start OS bring up in PetaLinux…

  • schematics for AES-ACC-U96-JTAG

    Hello, Could someone from Avnet publish the schematics of the AES-ACC-U96-JTAG JTAG pod for Ultra96, or at least the technical information required to make it work with OpenOCD or other open source JTAG solutions? If not, are there alternative JTAG and…

  • The Summer of FPGAs - Agenda

    Summer of FPGAs Main Agenda | Design Challenge | Essentials | Quiz | RoadTests | Tech Spotlights | Webinars | 2 Minute FPGA | Other Related Programs | Embedded | Manufacturers FPGAs are synonymous with artificial Intelligence, high performance…

  • New! Avnet Boards Xilinx Solutions Guide

    Hello! Looking for a new Xilinx SBC to play with or the best Xilinx Zynq or Zynq UltraScale+ SOM to use in your product? Can't decide what Avnet SOM or SBC is the best fit for your application? Avnet has just published a new Xilinx Solutions Guide: Avnet…

  • What Do You Think About Xilinx’s 16nm ZU1/2/3 InFO Package?

    Have you heard about Xilinx’s latest release in the 16nm line, the ZU1/2/3 InFO package? This package uses 60% less area and is roughly 70% thinner than standard Zynq UltraScale+ chip. InFO (for those that don’t know) stands for Integrated Fan-Out. This…

  • Using Avnet Build Scripts to Build a PetaLinux BSP (2020.1 and later)

    This is an update to the popular Using Avnet Build Scripts to Build a PetaLinux BSP (2019.2 and earlier) blog post. Like the Avnet HDL github repository of build scripts, IP, etc. for building the Vivado projects that are the hardware foundation for customers…

  • Avnet HDL git HOWTO (Vivado 2020.2 and later)

    This is an update to the popular Avnet HDL git HOWTO (Vivado 2020.1 and earlier) blog post. You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and UltraZed…

  • Linux QSPI Boot, Partitions, and Reboot, Oh My!

    Hacking the Devicetree to Achieve the Linux QSPI Boot Trifecta This is a tale of pain, grief, and redemption when working through strange Linux behavior and boot failures, and what happens when the devicetree doesn't match the underlying hardware. I recently…

  • Recent Fixes to PetaLinux QEMU Boot for Avnet SOMs and SBCs

    It recently came to our attention at Avnet that PetaLinux QEMU boot was broken for our MicroZed SOMs, and possibly also broken for PicoZed, UltraZed, MiniZed, and Ultra96-V2. After spending some time to dive in and debug this problem we discovered that…

  • How to Leverage Board Presets to Accelerate Your Vivado Design

    Note: This is one alternative for adding board definitions to the Xilinx tools the other option is documented here. Xilinx BoardStore to Automate Vivado Board Definitions for Avnet Boards For anyone just getting started with Xilinx Vivado, a good place…

  • Updating PMIC on Ultra96-V2 through the 2020.1 BSP!

    We have now released the 2020.1 BSP for both Ultra96-V2 and UltraZed EV with the PMIC programming utility built in! For the purposes of this blog, I am going to provide instruction on how to simply download the 2020.1 BSP as an SDcard image. You will…

  • Time Saving Tips and Tricks for Accelerating FPGA Builds

    Hi all, I was working through the update to the 2020.2 version of the Xilinx and realized there was a few small awesome things that we have included that might be of interest to the greater community! I also think that you could translate this information…

  • Big Changes Coming for Avnet git Repos for Zeds, UltraZeds, and Ultra96-V2

    We are currently working on PetaLinux 2020.2 BSPs for the Avnet MicroZed, PicoZed, and UltraZed SOMs and MiniZed and Ultra96-V2 SBCs As part of these BSP updates we are also taking the time to make some much needed and overdue changes to the HDL, PetaLinux…

  • Ultra96-V2 Dual Camera Mezzanine Petalinux Build Instructions

    As a follow up to the blog I posted on building the hardware design for the out of box image for the ON Semiconductor Dual Camera Mezzanine card, here are the instructions to complete the build with the Petalinux project. The original blog can be found…

  • Ultra96-V2 ON Semiconductor Dual Camera Mezzanine hardware build instructions

    I'm going to borrow heavily from my colleague Tom Curran and his excellent HDL howto blog ( Avnet HDL git HOWTO (Vivado 2020.1 and earlier) ). I highly recommend reading through that blog before continuing. I will modify it as needed to help you build…

  • FREE Xilinx Vitis 2019.2 Training for Ultra96-V2 (and update to the Ultra96-V2 BDF)

    Last year when Avnet released the Technical Training Courses for Ultra96 , the courses were based on Xilinx 2018.3 tools, which did not include Xilinx Vitis. This 2018.3 Ultra96 TTC Series includes 8 total days of training across 6 different introductory…

  • Minized - Vitis accleration 2019.2

    Hi! I have created this little tutorial how to prepare your Minized for some acceleration in Vitis 2019.2 Project is built based on Avnet BSP and shows whole platform creation process. Acceleration BSP is included in project , feel free to use your own…

  • Accelerating PetaLinux BSP Build Time

    Have you ever wished that your PetaLinux project didn't take so long to build? Have you ever wanted a way to make the build happen faster? Alas! There are simple steps to follow to accelerate your PetaLinux project build times. As much as a 50% reduction…

  • Using Avnet Build Scripts to Build a PetaLinux BSP (2019.2 and earlier)

    This blog post is a long overdue continuation of the " Avnet HDL git HOWTO " blog post I wrote last year. Like the Avnet HDL github repository of build scripts, IP, etc. for building the Vivado projects that are the hardware foundation for customers to…

  • Announcing New PetaLinux 2019.2 BSP for Ultra96-V2

    Hi Everyone, Avnet has just released the PetaLinux 2019.2 BSP for the Ultra96-V2 board : This BSP includes working WiFi and access point to ease configuration for connecting to the user's WLAN. Instructions for this can be found in the Ultra96-V2 Getting…

  • Tips for Integrating WiFi on the Ultra96-V2

    A key feature of Avnet's Ultra96-V2 board is its WiFi and Bluetooth connectivity that is made possible using the on-board ATWILC3000 module from Microchip. This module is IEEE 802.11 b/g/n plus Bluetooth 5 LE and is certified in more than 75 countries…

  • Avnet HDL git HOWTO (Vivado 2020.1 and earlier)

    You may know that Avnet provides PetaLinux BSPs and other reference designs for the Xilinx Zynq and Zynq UltraScale+ Zed SOMs (MicroZed, PicoZed, and UltraZed) and development boards (MiniZed and Ultra96), but did you also know that Avnet provides Xilinx…