• Zynq PS Spi and Quad Spi referance design tutorial Help

    I'm trying to make communicate between ps7_spi_0 and axi_quad_spi. This is block diagram. FCLK_CLK0 is 100 Mhz. SPI_0 is 166.666666 Mhz C code : /* * helloworld.c: simple test application * * This application configures UART 16550 to baud…
  • Tria Vitis Platforms — Adding support for ROS2

    Tria Vitis Platforms — Adding support for ROS2

    Introduction This project is part 5 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
  • Tria Vitis Platforms — Adding support for Hailo-8

    Tria Vitis Platforms — Adding support for Hailo-8

    Introduction This project is part 4 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
  • Tria Vitis Platforms — Adding support for Vitis-AI 3.5

    Tria Vitis Platforms — Adding support for Vitis-AI 3.5

    Introduction This project is part 3 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…
  • Tria Vitis Platforms -   Creating a Common Platform

    Tria Vitis Platforms -   Creating a Common Platform

    Introduction This project is part 2 of a 5 part series of projects, where we will progressively create AI enabled platforms for the following Tria development boards: ZUBoard Ultra96-V2 UltraZed-7EV These projects can be rebuilt using the…

  • Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): solve xsdb segmentation fault

    You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…

  • Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): connect to the USB debugger as a normal user

    You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…

  • Vivado, Vitis and PetaLinux on Windows Sublayer for Linux (WSL2): attach and detach your USB debugger

    You can run Vivado and Vitis on WSL2 . One reason to do that, is that you can run the provided build scripts as is. You 'll be able to recreate the source for the Pynq Base Vivado project, and Digilent's Vivado project for the Arty Z7 (and S7). It 'll…

  • in L3 Corner Track example. Why the flow buffer needs to be created everytime in loop?

    How can i reduce the execution time of "L3 Corner Track example" using my own video. I have observed in Vitis Analyzer that optical flow buffers are created in a loop which are adding more time to the execution process. I already managed to move other…

  • How to use Vitis HLS IP in Python Pynq overlay Environment.

    Hello everyone, happy new year. Please guys can you help me to fix my problem. I have programmed a HLS IP for using in vivado to transfer data from PL to PS. I am using pynq overlay. When i start the IP by writing in the register of the custom ip (0x0…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 2: software

    Part 2 of a little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. In post 1 , I show the Vivado design differences. Zynq uses…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 1: hardware

    A little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. The post focuses on the software / firmware aspect. How I migrated…
  • Vitis-AI 3.0 designs for Ultra96-V2 and ZUBoard

    Vitis-AI 3.0 designs for Ultra96-V2 and ZUBoard

    Avnet has just released a series of projects that builds up Vitis-AI 3.0 and ROS2 enabled designs for Ultra96-V2 and ZUBoard. Type Description ZUB1CG Links U96V2 Links Hackster 1 Building the foundational…
  • Arty S7 50 VGA Thermal Imaging Camera

    Arty S7 50 VGA Thermal Imaging Camera

    In this post we describe how to build a l ow resolution thermal imaging camera with VGA output. The solution is based on the Melexis MLX90640 IR Array , the Digilent's PmodVGA module, and the AMD-Xilinx Spartan-7 FPGA of the Digilent Arty S7 50 board…

  • How to write the contents of a text file to DDR RAM on the Arty S7-50 board (or any fpga)?

    I am trying to load a image directly to the DDR SDRAM on the Art S7 board. I have converted the jpg image into a txt file containing the integer RGB values for each pixel in separate lines. The file is as shown below: Then I created a block design…
  • Arty S7 50 ArtyBot ToF Sensor for Obstacle Avoidance. Vivado Hierarchical Blocks

    Arty S7 50 ArtyBot ToF Sensor for Obstacle Avoidance. Vivado Hierarchical Blocks

    Our Artybot already controls motors via PWM signals and has rotational speed and motor position feedback via magnetic sensors, can "see" colors and has a user interface with switches , buttons , r ed LEDs, RGB LEDs and an OLED display . In this tutorial…

  • 7 Ways to Leave Your Spartan-6, what have I learned

    I started working on my project ( post 1 and post 2 ) about a month ago. I had a bit of experience both with Xilinx/Amd Zynq SoCs as well as Altera/Intel Cyclone V SoCs. While working on the 7 Ways to Leave Your Spartan-6, I was able to explore the Spartan…
  • Arty S7 50 ArtyBot becomes Emubot, an educational robot for young children

    Arty S7 50 ArtyBot becomes Emubot, an educational robot for young children

    In this post I will introduce the Emubot project. Emubot is a simplified Logo turtle developed on the AMD-Xilinx Spartan-7 FPGA of the Digilent Arty S7 board. This simplified Logo turtle protoype with a Pmod OLED display module is aimed at children and…

  • Recreate the Arty-S7 Out of Box design - part 2: MicroBlaze Firmware rebuild

    This is part 2 of the instructions to build the Arty-S7 Out-of-box experience from source. In part 1 , I showed how to get the Vivado project created, and regenerate the FPGA design. That exercise delivers the full hardware design, but not the firmware…
  • Arty S7 50 ArtyBot - Bot Application Framework

    Arty S7 50 ArtyBot - Bot Application Framework

    In this post I describe the Bot Application Framework that I have prepared for the Digilent Arty S7 based bot and provides an overview of the Arty S7 Bot Application Framework , its architecture, components, and usage model. This post is part 7 of my…
  • Arty S7 50 ArtyBot Pulse Width Modulation (PWM) for Motor Speed Control

    Arty S7 50 ArtyBot Pulse Width Modulation (PWM) for Motor Speed Control

    In the previous blogs in this series for the " 7 Ways to Leave Your Spartan-6 " program we learned how to use the AMD-Xilinx Vivado and the AMD-Xilinx Vitis . We used Vivado for creating hardware designs for the Arty S7 board with a Hardware Design Language…
  • Arty S7 - Imaging System Part 1: Microblaze Hello world

    Arty S7 - Imaging System Part 1: Microblaze Hello world

    For the 7 ways to leave your Spartan-6 FPGA program, I wanted to explore the use of Spartan-7 in an imaging system. I have some experience working with video streams on Zynq-7000 FPGAs (which I love!), but I never tried the same on Spartan series FPGAs…
  • Arty S7 50 ArtyBot How to Store MicroBlaze Program in the Quad-SPI Flash from Vivado

    Arty S7 50 ArtyBot How to Store MicroBlaze Program in the Quad-SPI Flash from Vivado

    We want our Artybot to be autonomous. Until now every time we turned off the Arty S7 50 board we lost the program loaded in the board's RAM. This guide will show you how to store a Microblaze program in the SPI Flash on your Arty S7 50 device. Storing…
  • Arty S7 50 ArtyBot Custom AXI4 Lite IP Peripheral for Sensing Motor Rotational Speed

    Arty S7 50 ArtyBot Custom AXI4 Lite IP Peripheral for Sensing Motor Rotational Speed

    In this tutorial we will learn how to create a custom AXI4 Lite IP Peripheral implementing a tachometer. We will add two quadrature encoders with Hall effect sensors to the mini plastic gear motors of the ArtyBot. The tachometer will enable the robot…
  • Arty S7 50 Rapid Prototyping - Environmental Monitor

    Arty S7 50 Rapid Prototyping - Environmental Monitor

    For the 7 Ways to Leave Your Spartan-6 program I am writing a series of tutorials using the Arty S7 50 . In the previous blogs I did two introductory tutorials to create a simple hardware-only project and another baremetal one on a MicroBlaze softprocessor…