Almost a year ago, I received a very nice surprise from e14. Unfortunately, until now it sat aside, waiting for some love. This is going to change soon!
The board
The CMOD S7 from Digilent is a very nice little board, fitted with a Spartan 7 FPGA…
I just discovered that AMD have decided to support the Spartan6 range for a good few years more.
This is good news for quite a few I should think since the previous line that everyone should move to the Spartan 7 was not universally popular.
The announcement…
Hi,
I am Arun. I am a hardware Engineer with 8years experience in in IoT and RF schematic and pcb design. I am new in FPGA design. How can I start my career in FPGA based design? Kindly advice the initial steps.
Introduction
In the previous blog, FPGA ADSR envelope generator for sound synthesis , we discussed ADSR envelope generators. The data input to the ADSR module was hardcoded. It would be nice to be able to enter the step increments with knobs for each…
ADSR envelope generator for sound synthesis.
In the previous blog we implemented a Direct Digital Frequency Synthesis module (DDFS ) that can generate an unmodulated audio-frequency tone. In this blog we will implement an ADSR (attack-decay-sustain…
DDFS - Direct Digital Frequency Synthesis
DDFS is a digitally-controlled method of generating multiple frequencies from a reference frequency source. DDFS is a method of producing a tunable digital or analog waveform. First the data points of the waveform…
element14's 7 Ways to Leave Your Spartan-6 Program concluded several months ago. Twenty-five members participated in the program. Overall, they produced an incredible number of blogs. It was interesting to read all the comments, too. As an observer, I…
Finishing up with combinational circuit design exercises in System Verilog. This time we are going to do exercises on another representation of numbers, BCD (binary-coded decimal format)
Table of Contents
Binary-coded decimal
1-digit BCD…
RTL Combinational Circuit - Design Examples - Hex-Digit to Seven-Segment LED Decoder RTL Combinational Circuit
We have been reviewing the main constructs and operators for designing combinational logic circuits with the SystemVerilog HDL. Let's apply…
In the previous chapter we reviewed some of the main SystemVerilog operators that allow us to describe the operation of combinational logic circuits. In this chapter we will review some of the SystemVerilog constructs that allow us to describe parts of…
I continue my series of notes on SystemVerilog as I learn. In this case I dedicate the study notes to Verilog operators as an introduction to combinational circuits. I'll cover always blocks and other routing constructs in a later blog.
Table of Contents…
I am learning SystemVerilog HDL. I started reading the book FPGA Prototyping By SystemVerilog Examples . These are my study notes and what I am learning about SystemVerilog. My idea is to do exercises with the Digilent Arty S7 50 board obtained in the…
I was wondering if I could somehow do some crypto mining on my Arty S7-50 board. I know that it might not be much profitable. ASICs are better for this job. But I want to try it just for education purposes.
What does the members think? Will it be profitable…
Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1
Build a project with the Arty S7 - Line Follower Robot (Part 1) - Introduction
Build a project with the Arty S7 - Line Follower Robot (Part 2) - Setting up Vivado 2019.2 and Demo program…
Reasons to switch from Spartan-6 to Spartan-7 FPGAs #1
Build a project with the Arty S7 - Line Follower Robot (Part 1) - Introduction
Build a project with the Arty S7 - Line Follower Robot (Part 2) - Setting up Vivado 2019.2 and Demo program…
Hello everyone. Today it is deadline of 7 Ways to Leave Your Spartan-6 FPGA . Today I completed quiz (with one mistake made) and post blog post about my project. My performance in this competition is not as good as I originally expected. It was mainly…
Hello everyone. I welcome you to this blog post describing my project as part of 7 Ways to Leave Your Spartan-6 FPGA contest.
In this blog post I will describe my core project as part of this competition. As part of this competition I originally promised…
FPGA was a completely new thing to me before participating in this program. I learned a lot of things while writing blogs for this program. The list of all the blogs is given below:
Spartan-6 VS Spartan-7 (Comparison)
Getting Started with Arty S7…
Introduction: In my project , I am sending the blurred image to my PC over uartlite. I had to put some delay (50 us) between sending consecutive data packets. Due to the large size of the image, it takes around 8-9 mins to transfer the image. Maybe reducing…
Introduction: In my previous blog , I learned how to use the XADC block in my design. I am thinking of using the XADC alongwith the IR sensor that I used in that blog in my Image Processing project . I will use this IR sensor to toggle between various…
Introduction
As part of the 7 Ways to Leave Your Spartan-6 FPGA roadtest , I have been exploring sensors that can be connected to the Arty-S7 for audio applications. For the current project, I am focussing on the following sensors
Pmod I2S2 - Used…
In this post we describe how to build a l ow resolution thermal imaging camera with VGA output. The solution is based on the Melexis MLX90640 IR Array , the Digilent's PmodVGA module, and the AMD-Xilinx Spartan-7 FPGA of the Digilent Arty S7 50 board…
In my last two blogs, I talked only about VHDL codes and the implementation of digital logic design in Vivado. In this blog, I will be working on the hardware aspects.
I received the Arty-S7 board from e14 for the Spartan_Migration challenge. I will…
Introduction: The Arty S7 board comes with an on board ADC. The XADC core within the Spartan-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. The analog pins can be used to read analog values. I have a IR sensor which…
Introduction: After learning about various things that can be done on Arty S7-50, I think I am now ready to put all my learnings together in one project. In this blog, I will try to implement a basic image processing algorithm (blurring an image) on the…
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