Hii all,
This is me first time posting here on element14. I recently completed a Hardware Description of a part of a processor in Verilog. In this mini project, I ensured the datapaths, added 7 registers ( 6 normal and 1 special). The special register…
Hello,
I have the PYNQ-Z2 board, and using Vivado 2019.2 and PYNQ Image V2.4
I am working on accelerating canny edge detection on PL and then connecting it to PS to do lane detection using hough transform
Input is from HDMI-in, output goes to HDMI…
I have trained weights and biases from a CNN network for different layers. I have converted those data into fixed point 16-bit binary format and saved them as .txt files for different convolutional layers. Since the data files are too large to accommodate…
I'm trying to develop a RISC-V processor in Verilog and SystemVerilog and then later want to synthesize and test it on FPGA. I'm currently using Xilinx Vivado to write and debug code. But, the issue which I'm facing is that as my processor is scaling…
Hi,
I am Arun. I am a hardware Engineer with 8years experience in in IoT and RF schematic and pcb design. I am new in FPGA design. How can I start my career in FPGA based design? Kindly advice the initial steps.
Finishing up with combinational circuit design exercises in System Verilog. This time we are going to do exercises on another representation of numbers, BCD (binary-coded decimal format)
Table of Contents
Binary-coded decimal
1-digit BCD…
We continue with combinational circuit design exercises in SystemVerilog. This time we are going to do exercises on number representation formats using a simplified floating point format.
Table of Contents
Floating point arithmetic
Simplified…
RTL Combinational Circuit - Design Examples - Barrel Shifter RTL Combinational Circuit
We continue experimenting with RTL Combinational Circuits designed in SystemVerilog. In this blog we are going to design circuits around a very useful circuit that…
RTL Combinational Circuit - Design Examples - Hex-Digit to Seven-Segment LED Decoder RTL Combinational Circuit
We have been reviewing the main constructs and operators for designing combinational logic circuits with the SystemVerilog HDL. Let's apply…
In the previous chapter we reviewed some of the main SystemVerilog operators that allow us to describe the operation of combinational logic circuits. In this chapter we will review some of the SystemVerilog constructs that allow us to describe parts of…
I continue my series of notes on SystemVerilog as I learn. In this case I dedicate the study notes to Verilog operators as an introduction to combinational circuits. I'll cover always blocks and other routing constructs in a later blog.
Table of Contents…
I am learning SystemVerilog HDL. I started reading the book FPGA Prototyping By SystemVerilog Examples . These are my study notes and what I am learning about SystemVerilog. My idea is to do exercises with the Digilent Arty S7 50 board obtained in the…
The enhanced Pulse Width Modulation (ePWM) IP creation has only one objective, to reduce the processor time required for direction control in the motor driver. It is based on a 32-bit signed int data type and can handle positive and negative values. A…
Introduction
When I decided to participate in the "7 Ways to Leave Your Spartan-6 FPGA" contest, I knew it would take a lot of effort. The board is a really great piece of technology and it was an opportunity for me to get acquainted with FPGA technology…
This is a continuation of my previous post . If you haven't seen it yet, I would strongly recommend taking a look, since we'll be continuing from where we left off. Everything mentioned and used in the project is located in my GitHub repo .
Previously…
I started my FPGA journey with VHDL. Hence, I'm quite comfortable with VHDL. I tried learning Verilog, but it seems redundant to me as I already knew one HDL, so I gave up on learning Verilog.
However, while pursuing my master's, I saw that Verilog…
Hello everyone, I'm among the selected challengers for the 7 ways to leave your Spartan-6 design challenge. Firstly I would like to thank the e14 community for providing me with the Arty S7 FPGA board. This will be my first FPGA board, having one of the…
I found these discussion forums:
1BitSquared Discord
Digilent Forums
FPGA Subreddit
Learning resources:
f pga4fun.com
fpgacpu.ca
Nandland
YouTube Channels:
After Hours Engineering
Piotr Esden-Tempski
If you know of…
This document is based on “Migrating Spartan-6 Designs to 7 Series & Beyond” document of Adam Taylor. There are a lot of interesting features in the new family and development tools. To describe these differences, I will use two cookies: A spartan 6-based…
I received the Digilent Arty S7 50 Board for the 7 Ways to Leave Your Spartan-6 FPGA program. In this blog I describe what the first power up of the board is like and then a small tutorial on how to create your first Hardware-Only design.
"7 Ways…
Hello everyone.
Yesterday I received Arty S7 Board for the 7 Ways to Leave Your Spartan-6 FPGA contest.
Board is offered available in two variants differing in FPGA. We received the better variant with Spartan XC7S50 FPGA featuring 52160 logic cells…
Hi Guys! I was the beginner learn about the FPGA. Is that anyone can tell me, why this device are more usefull rather than another devices to run the project (especially in computer and biomedical engineering)? maybe could be compare with the PIC or another…
This is not a strictly FPGA question... but related. What program do you guys recommend to find critical paths in a verilog circuit file? As program inputs I would like to give in a technology mode a verilog file and a couple of circuit sites, and as…
Simple code in Verilog for controll a seven segment display by Arty S7 board Music: Eric Skiff - Song Name - Resistor Anthems - Available at http://EricSkiff.com/music
