• Help Object detection and tracking with color space conversion and morph operators

    Help Object detection and tracking with color space conversion and morph operators I want to implement with boundingbox the opencv example code on the link: https://www.opencv-srf.com/2010/09/object-detection-using-color-seperation.html …

  • Install Vivado, Vitis and PetaLinux on Windows Sublayer for Linux

    I'm installing the Vitis and Vivado tools on a WSL instance. Most of tutorials on scripting and build automated are for Linux. I want to test this out. My WSL runs Ubuntu 20.04.3 LTS. I was surprised that WSL actually shows the install GUI. I thought…

  • How to build Xilinx Default HDL Project for zcu102 in Window?

    Video link: https://studio.youtube.com/video/nSbfVxOD5vk/edit Courtesy to: https://wiki.analog.com/resources/fpga/docs/build Prerequisites: Prerequisites: Vivado installed Steps to build: Cygwin installation https://www.cygwin.com…

  • in L3 Corner Track example. Why the flow buffer needs to be created everytime in loop?

    How can i reduce the execution time of "L3 Corner Track example" using my own video. I have observed in Vitis Analyzer that optical flow buffers are created in a loop which are adding more time to the execution process. I already managed to move other…

  • How to use Vitis HLS IP in Python Pynq overlay Environment.

    Hello everyone, happy new year. Please guys can you help me to fix my problem. I have programmed a HLS IP for using in vivado to transfer data from PL to PS. I am using pynq overlay. When i start the IP by writing in the register of the custom ip (0x0…

  • Blinking a LED with PYNQ in Kria KV260 / KR260

    1. Introduction In this article, we will install PYNQ in Ubuntu 22.04 and then I will show you how to do a simple LED blinking using Python in PYNQ. 2. Installing PYNQ in KV260 The Xilinx/Kria-PYNQ is the main repository for everything related…

  • Booting Ubuntu 22.04 in Kria KV260 (or KR260)

    1. Introduction In the previous article , we looked at how we can upgrade the Kria SOM firmware to make it able to boot Ubuntu 22.04 (without the firmware, it can only boot Ubuntu 20.04). In this article, we will build on that and boot the OS. Booting…

  • Kria (KV260/KR260) firmware update for booting Ubuntu 22.04

    1. Introduction KV260 and KR260 firmware by default cannot boot the Ubuntu 22.04. Therefore, an update to the firmware is necessary. In this article, I will show you how to update the firmware step by step. I have the following setup. Petalinux…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 2: software

    Part 2 of a little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. In post 1 , I show the Vivado design differences. Zynq uses…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 1: hardware

    A little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. The post focuses on the software / firmware aspect. How I migrated…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

    Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

    Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal . yepe has a goal to create a set of signals for an ultrasone pulse generator. Status after Post 2 In Post 2,…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

    Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

    Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach . yepe has a goal to create a set of signals for an ultrasone pulse generator. Status after Post 1 In Post 1, we got the…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach

    Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach

    yepe has to resolve this problem for a project assignment: Hi Jan Cumps, I hope you don't mind if I ask a question regarding the PYNQ half-bridge PWM driver. I am working on a student project for school and I need to drive a half-bridge for…

  • How can I choose FPGA?

    Former Member
    Former Member
    Hi, I am Arun. I am a hardware Engineer with 8years experience in in IoT and RF schematic and pcb design. I am new in FPGA design. How can I start my career in FPGA based design? Kindly advice the initial steps.

  • Pynq Version 3 released

    Pynq has released version 3 in October. Highlights (from the release notes ): All overlays built with Vivado 2022.1 Linux kernel and build updated to Petalinux 2022.1 Productivity additions - software Updated to Python 3.10 Updated…

  • Vivado and Zynq: TRI-STATE help

    I'm trying to write i2c code for Zynq, in VHDL. I have difficulties creating a TRI-STATE pin. The output logic should be: the pin is either pulled down to 0, or open-collector . I have a pull-up resistor between that pin and VCC (3.3 V). I'm expecting…

  • Testing a VHDL LCD matrix display driver

    I'm going to try out a VHDL driver for the Hitachi HD44780 LCD driver. I've ported it for several microcontrollers (TI Hercules , Maxim MAX32660 ) and a Linux device in the past. I was going to write a VHDL driver, but found a few potential candidates…

  • Make a Linux executable for a PYNQ board with Vitis - and debug it

    Zynq controllers can run Linux. Xilinx uses Vitis - an Eclipse derivate - as the development platform for the ARM part of the Zynq. We'll use it to build - and debug! - a native Linux program. Vitis knows how to program for the ARM processors (all Zynq…

  • VHDL: Convert a Fixed Module into a Generic Module for Reuse

    The goal of this post is turn a fixed VHDL design into a configurable one. Change a fixed RAM IP into RAM that can be sized, without changing source or logic. I use michaelkellett 's VHDL RAM Memory design before: use RAM design for Altera Cyclone on…
    • memory_ram_dma_vivado_project_and_jupyter_notebook.zip

  • Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ

    In this series of 2 blogs, I'm trying to sample the ADC at high speed and move the samples to memory fast. The goal is to achieve the highest speed - 1 MSPS ( Megasamples per second = millions of samples per second ). In the previous article , I checked…

  • Use the ZYNQ XADC with DMA part 1: bare metal

    The Zynq family has an on-board 12 bit ADC, in the FPGA part of the silicon. They call it the XADC. It can sample internal rails and temperatures. There's also the possibility to use external inputs. In this series of 2 blogs, I'm trying to sample the…

  • PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software

    I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience. Use the Accelerated function in Software In part 1, we made the hardware accelerated…

  • PYNQ version 2.7 (Austin) is released

    Yesterday, the PYNQ community released version 2.7 of the the PYNQ OS. SD Card images are available for download. What's new: Vivado, Vitis HLS version 2020.2 Python 3.8 Additional boards supported Composable overlay pipeline Petalinux 2020…

  • Learning Xilinx Zynq: Interrupt ARM from FPGA fabric

    You can interrupt the Zynq ARM side with a signal coming out of the FPGA part of the chip. In this post, I test this. The FPGA part has a few blocks that will generate interrupts. In a Jupyter notebook, I'll try to show that they are detected by the…

  • Zynq Pynq Quadrature Oscillator with variable clock frequency

    A quadrature clock, in VHDL and Vivado. With Jupyter notebook to test it. It's for training purposes, can be used as mixer for radio signals. Related blog: https://www.element14.com/community/groups/fpga-group/blog/2021/08/31/learning-xilinx-zynq-...
    • https://youtube.com/watch?v=bhCdLr668E0
    • View