• Install Vivado, Vitis and PetaLinux on Windows Sublayer for Linux

    I'm installing the Vitis and Vivado tools on a WSL instance. Most of tutorials on scripting and build automated are for Linux. I want to test this out. My WSL runs Ubuntu 20.04.3 LTS. I was surprised that WSL actually shows the install GUI. I thought…

  • Design and Development of Keyword Spotting Module using MFCC algorithm for Robotic Movement on PYNQ-Z1 Board

    Introduction Current Scenario: Is a spoken word audio dataset intended to aid in the development and evaluation of keyword recognition systems? Explains the appeal of this task as a challenge and the need for a unique dataset that is distinct from the…

  • PYNQ-Z2 Base Overlay Video Modification

    Hello, I have the PYNQ-Z2 board, and using Vivado 2019.2 and PYNQ Image V2.4 I am working on accelerating canny edge detection on PL and then connecting it to PS to do lane detection using hough transform Input is from HDMI-in, output goes to HDMI…

  • PYNQ Z2 FPGA

    Hello Everyone I am Saurav and I am trying to learn PYNQ Z2 FPGA board. I dont know the correct way to reupload python code from Jupyter to Z2 board, Suppose I made some changes in my code and I want to check that code how should I do that The steps…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 2: software

    Part 2 of a little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. In post 1 , I show the Vivado design differences. Zynq uses…

  • Port a VHDL design from AMD Zynq & Pynq to Spartan-7 & MicroBlaze - part 1: hardware

    A little double post to document the porting of a small FPGA design from a Zynq with ARM + Linux + Pynq + Python to a smaller Spartan with MicroBlaze soft controller + bare metal. The post focuses on the software / firmware aspect. How I migrated…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

    Learning AMD Zynq: a project to generate a set of PWM signals. 3 - add GATE signal and demodulation clock

    Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal . yepe has a goal to create a set of signals for an ultrasone pulse generator. Status after Post 2 In Post 2,…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

    Learning AMD Zynq: a project to generate a set of PWM signals. 2 - add overall control block, delay and pulse signal

    Continuation of Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach . yepe has a goal to create a set of signals for an ultrasone pulse generator. Status after Post 1 In Post 1, we got the…
  • Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach

    Learning AMD Zynq: a project to generate a set of PWM signals. 1 - problem statement and possible approach

    yepe has to resolve this problem for a project assignment: Hi Jan Cumps, I hope you don't mind if I ask a question regarding the PYNQ half-bridge PWM driver. I am working on a student project for school and I need to drive a half-bridge for…

  • Pynq Version 3 released

    Pynq has released version 3 in October. Highlights (from the release notes ): All overlays built with Vivado 2022.1 Linux kernel and build updated to Petalinux 2022.1 Productivity additions - software Updated to Python 3.10 Updated…

  • PYNQ - Interactive C++ on the Kria-SoM in Jupyter Lab

    I saw this post by Shane Fleming on the PYNQ discussion board that I thought would be of interest to the PYNQ users in the E14 community: Interactive C++ on the Kria SoM in Jupyter Lab It caught my eye because up to this point I haven't tried interactive…

  • PYNQ Now Available for the Kria KV260 Vision AI Starter Kit

    Great news! PYNQ is now supported on the Xilinx Kria SOM PYNQ Now Available for the Kria KV260 Vision AI Starter Kit https://github.com/Xilinx/Kria-PYNQ

  • Make a Linux executable for a PYNQ board with Vitis - and debug it

    Zynq controllers can run Linux. Xilinx uses Vitis - an Eclipse derivate - as the development platform for the ARM part of the Zynq. We'll use it to build - and debug! - a native Linux program. Vitis knows how to program for the ARM processors (all Zynq…

  • VHDL: Convert a Fixed Module into a Generic Module for Reuse

    The goal of this post is turn a fixed VHDL design into a configurable one. Change a fixed RAM IP into RAM that can be sized, without changing source or logic. I use michaelkellett 's VHDL RAM Memory design before: use RAM design for Altera Cyclone on…
    • memory_ram_dma_vivado_project_and_jupyter_notebook.zip

  • Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ

    In this series of 2 blogs, I'm trying to sample the ADC at high speed and move the samples to memory fast. The goal is to achieve the highest speed - 1 MSPS ( Megasamples per second = millions of samples per second ). In the previous article , I checked…

  • Use the ZYNQ XADC with DMA part 1: bare metal

    The Zynq family has an on-board 12 bit ADC, in the FPGA part of the silicon. They call it the XADC. It can sample internal rails and temperatures. There's also the possibility to use external inputs. In this series of 2 blogs, I'm trying to sample the…

  • PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors

    This is a supporting post for Part 2: Add the Accelerated IP to a Vivado design . I'm untangling the different data streams. There are 3 types of data exchanged between the FPGA and ARM parts of the Zynq: "Business Data": the inputs and outputs to…

  • PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software

    I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience. Use the Accelerated function in Software In part 1, we made the hardware accelerated…

  • PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design

    I'm following the 3-part using a HLS stream IP with DMA training on the PYNQ community. This blog will not repeat the steps. The goal is to document the experience. Register the IP and Use it in Vivado In part 1, we made the hardware accelerated function…

  • PYNQ version 2.7 (Austin) is released

    Yesterday, the PYNQ community released version 2.7 of the the PYNQ OS. SD Card images are available for download. What's new: Vivado, Vitis HLS version 2020.2 Python 3.8 Additional boards supported Composable overlay pipeline Petalinux 2020…

  • Learning Xilinx Zynq: Interrupt ARM from FPGA fabric

    You can interrupt the Zynq ARM side with a signal coming out of the FPGA part of the chip. In this post, I test this. The FPGA part has a few blocks that will generate interrupts. In a Jupyter notebook, I'll try to show that they are detected by the…

  • Zynq Pynq Quadrature Oscillator with variable clock frequency

    A quadrature clock, in VHDL and Vivado. With Jupyter notebook to test it. It's for training purposes, can be used as mixer for radio signals. Related blog: https://www.element14.com/community/groups/fpga-group/blog/2021/08/31/learning-xilinx-zynq-...
    • https://youtube.com/watch?v=bhCdLr668E0
    • View

  • Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency

    This post is a follow up on a previous article to generate a quadrature clock for shabaz 's Software Defined Radio (SDR) Experiment Board . It's a circuit with 4 PWM outputs that are each 90° shifted. I'm adding programmable frequency control. Without…

  • PYNQ-Z2 Workshop Series: FPGA Experiments With Xilinx Pynq-Z2

    PYNQ-Z2 is a FPGA development board, intensively designed to support PYNQ, an open-source framework that enables embedded programmers to explore the possibilities of Xilinx ZYNQ SoCs without having to design programming logic circuits. Benefiting from…

  • Learning Xilinx Zynq: VHDL based PWM generator with scroll wheel control

    VHDL PWM generator with dead band support, 1.5 MHz VHDL scroll wheel decoder to control duty cycle Jupyter notebook shows duty cycle on a progress bar With Vivado, PYNQ for element14 blog: https://www.element14.com/community/groups/fpga-group/blog...
    • https://youtube.com/watch?v=kF1rS_YKuKQ
    • View