• Affordable Versal parts and their penetration in hobbyist circles

    Good day all, It's been a while since relatively affordable Versal boards came around - at least two sub-$1000 parts from reputable suppliers are available, as well as very interesting board that combines AMD Ryzen with Versal Edge device (that's a…

  • The Art of FPGA Design - Post 40

    Instantiating the DSPFP32 the Easy Way The final thing we need to use the new Versal DSPFP32 hardened floating point primitive is a way to access them through VHDL code. While it would be very nice to be able to infer the primitives, especially since…

  • The New DSPFP32 Primitive in Versal FPGAs

    The New DSPFP32 Primitive in Versal FPGAs The DSP primitive in the latest Versal FPGA family is called DSP58 and it already has a number of improvements over the latest DSP48 flavors, mainly an increase from 27x18 signed multiplier and 48-bit post adder…

  • The Art of FPGA Design - Post 38

    VHDL-2008 FP32 Support in Vivado VHDL-2008 introduced native support for floating point types with FLOAT, which is an arbitrary precision floating point type. While you can define generic modules with ports of unconstrained FLOAT type, or any actual…

  • FPGA and DSP ep. 4: Polyphase Filters

    Hello there, I just posted a video on YouTube about Polyphase filters. You can check it out here: You don't have permission to edit metadata of this video. …
  • Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12

    Fast VHDL CORDIC Sine and Cosine Component on Lattice XP2 Device Using Diamond 3.12

    Introduction This is still work in progress - I've only reached the simulation phase and haven't tried it on a device yet - but I thought it might be of some interest. Back when I did my 'Making Waves' blogs [1], I implemented a fast, unrolled, pipelined…
  • Quadrature Sinewave Generator on Lattice XP2 using Brevia 2 Development Board

    Quadrature Sinewave Generator on Lattice XP2 using Brevia 2 Development Board

    Introduction Some more simple DSP [digital signal processing] stuff with my lovely little Lattice Brevia-2 board with its XP2 FPGA. A couple of years back, I did a collection of blogs called 'Waves' using this board (see the links at the end). For…
  • 7 Ways to Leave Your Spartan-6 project: FPGA polarimeter part 2

    7 Ways to Leave Your Spartan-6 project: FPGA polarimeter part 2

    This is a continuation of my previous post . If you haven't seen it yet, I would strongly recommend taking a look, since we'll be continuing from where we left off. Everything mentioned and used in the project is located in my GitHub repo . Previously…

  • 基于DSP和FPGA的实时图像压缩系统设计

    目前使用的图像采集系统输入信号通常为PAL或者NTSL制式的CVBS复合信号，压缩速度25帧/s(PAL)或者30帧/s(NTSC)。但在工业控制、航天以及安防领域，有时需要监测快速移动的目标，或者瞬间发生的物理现象，事后还要对数据进行分析、处理。为了提高测量精度，通常需要采用高频帧图像采集系统。本文针对某Camera Link接口的图像传感器，设计了一个高频帧图像采集系统，该系统能够每秒采集100帧，并对其进行JPEG压缩，压缩完的数据通过RS422传输至远处的监测系统。 1 系统工作原理及硬件设计…

  • 数字电路设计方案的比较与选择

    数字信号处理技术和大规模集成电路技术的迅猛发展,为我们设计数字电路提供了新思路和新方法。当前数字系统设计正朝着速度快、容量大、体积小、重量轻的方向发展。DSP和FPGA技术的发展使这一趋势成为可能和必然。 和计算机一样,数字信号处理的理论从60年代崛起以来,到80年代DSP产生,它飞速发展改变了信号处理的面貌。今天DSP已广泛应用在语音、图像、通讯、雷达、电子对抗、仪器仪表等各个领域。DSP起了十分关键的作用,成为数字电路设计的主要方法。 二十世纪80年代以来,一类先进的门阵列——FPGA的出现…

  • The Art of FPGA Design Season 2 - Post 18

    Multichannel Symmetric FIRs In the last two posts we have considered the case when the FPGA clock frequency is faster than the FIR sample rate. The ratio between the system clock and the data sample rate is called the overclocking factor M. We have seen…

  • The Art of FPGA Design Season 2 - Post 17

    Multichannel and Overclocking FIRs - The Single Rate Symmetric Case In the last post I created an overclocked or semi-parallel implementation of a systolic, non-symmetric FIR, where each DSP48 in the chain implements M taps of the filter. The filter sample…

  • The Art of FPGA Design Season 2 - Post 16

    Multichannel and Overclocking FIRs - The Single Rate non-Symmetric Case We are looking now at the case of the single rate FIR filter where the sample rate is a sub-multiple of the FPGA clock rate. For example, let's say that the input and output sample…

  • The Art of FPGA Design Season 2 - Post 15

    Taking advantage of coefficient symmetry in Polyphase FIRs We have seen in previous posts that when the FIR coefficients are symmetric, we can use a DSP48 feature called a pre-adder and reduce the number of multipliers required in half. Essentially, an…

  • The Art of FPGA Design Season 2 - Post 14

    Polyphase Decimators The Polyphase Decimator FIR is the dual structure of the Polyphase Interpolator. The basic idea is that you can reduce the sample rate of a signal by a factor of M if you keep only one out of every M samples. This only works if the…

  • The Art of FPGA Design Season 2 - Post 13

    Polyphase Interpolators In the previous post we have looked at and important class of FIR filters, namely Polyphase architectures, which are extensively used for changing the sample rate of a signal by and integer factor, a process called interpolation…

  • The Art of FPGA Design Season 2 - Post 12

    Polyphase FIRs The half-band FIR is just one particular case of a larger class of FIR filter implementations called polyphase structures. The basic idea is to split the sum of products we need to compute for every filter output sample into multiple sub…

  • The Art of FPGA Design Season 2 - Post 11

    The Single Rate Half-Band FIR Decimator A decimating filter will reduce the sample rate of a signal, while preventing aliasing. Decimation by a factor of 2x is achieved by simply throwing out every second input sample. For this to work the input data…

  • The Art of FPGA Design Season 2 - Post 10

    The Single Rate Half-Band FIR Interpolator In the previous post we looked at the single rate half-band FIR, a particular type of odd-symmetric FIR, where almost half of the filter coefficients are zero. Not computing multiplications with these zero coefficients…

  • The Art of FPGA Design Season 2 - Post 9

    The Single Rate Half-Band FIR We have started by looking at the most general version of an FIR filter. From a mathematical point of view, this is all that is needed. There are countless variations, like the symmetric versions, both odd and even, they…

  • The Art of FPGA Design Season 2 - Post 8

    The Single Rate symmetric FIR, low latency transposed architecture The question we need to answer now is this - for those applications that require very low latency FIRs is there a way to avoid the increase in latency proportional to the filter order…

  • The Art of FPGA Design Season 2 - Post 7

    The Single Rate odd-symmetric FIR In the last post we have examined the even-symmetric FIR, a filter of order N=2*K. The main conclusion was that we only need K DSP48s to implement such a filter, and we came up with a basic building block that is both…

  • The Art of FPGA Design Season 2 - Post 6

    The Single Rate even-symmetric FIR We have looked so far at the simplest and most generic FIR possible, the single rate non-symmetric FIR filter. But many FIR filter implementations have more particular structures and taking advantage of these can improve…

  • The Art of FPGA Design Season 2 - Post 5

    The Single Rate non-symmetric FIR, direct and transpose architectures As I mentioned earlier, the single rate non-symmetric FIR filter has two possible implementations, the direct and the transpose forms. We will now apply again the retiming and pipeline…

  • The Art of FPGA Design Season 2 - Post 4

    Register pushing and the pipeline cut It should be clear by now that a direct implementation of the DSP algorithm is not good enough. Every single individual computation block, the adders and the multipliers, will require pipeline registers and there…