• The Art of FPGA Design - Post 40

    Instantiating the DSPFP32 the Easy Way The final thing we need to use the new Versal DSPFP32 hardened floating point primitive is a way to access them through VHDL code. While it would be very nice to be able to infer the primitives, especially since…

  • The New DSPFP32 Primitive in Versal FPGAs

    The New DSPFP32 Primitive in Versal FPGAs The DSP primitive in the latest Versal FPGA family is called DSP58 and it already has a number of improvements over the latest DSP48 flavors, mainly an increase from 27x18 signed multiplier and 48-bit post adder…

  • The Art of FPGA Design - Post 38

    VHDL-2008 FP32 Support in Vivado VHDL-2008 introduced native support for floating point types with FLOAT, which is an arbitrary precision floating point type. While you can define generic modules with ports of unconstrained FLOAT type, or any actual…

  • The Art of FPGA Design - Post 37

    Recent Advances in Vivado VHDL-2008 Support Previous posts in this blog were made in the 2018-2019 period. Some of the issues presented were an attempt to work around VHDL-2008 support limitations in Vivado at that point in time. Since then, significant…

  • The Art of FPGA Design Season 2 - Post 18

    Multichannel Symmetric FIRs In the last two posts we have considered the case when the FPGA clock frequency is faster than the FIR sample rate. The ratio between the system clock and the data sample rate is called the overclocking factor M. We have seen…

  • The Art of FPGA Design Season 2 - Post 17

    Multichannel and Overclocking FIRs - The Single Rate Symmetric Case In the last post I created an overclocked or semi-parallel implementation of a systolic, non-symmetric FIR, where each DSP48 in the chain implements M taps of the filter. The filter sample…

  • The Art of FPGA Design Season 2 - Post 16

    Multichannel and Overclocking FIRs - The Single Rate non-Symmetric Case We are looking now at the case of the single rate FIR filter where the sample rate is a sub-multiple of the FPGA clock rate. For example, let's say that the input and output sample…

  • The Art of FPGA Design Season 2 - Post 15

    Taking advantage of coefficient symmetry in Polyphase FIRs We have seen in previous posts that when the FIR coefficients are symmetric, we can use a DSP48 feature called a pre-adder and reduce the number of multipliers required in half. Essentially, an…

  • The Art of FPGA Design Season 2 - Post 14

    Polyphase Decimators The Polyphase Decimator FIR is the dual structure of the Polyphase Interpolator. The basic idea is that you can reduce the sample rate of a signal by a factor of M if you keep only one out of every M samples. This only works if the…

  • The Art of FPGA Design Season 2 - Post 13

    Polyphase Interpolators In the previous post we have looked at and important class of FIR filters, namely Polyphase architectures, which are extensively used for changing the sample rate of a signal by and integer factor, a process called interpolation…

  • The Art of FPGA Design Season 2 - Post 12

    Polyphase FIRs The half-band FIR is just one particular case of a larger class of FIR filter implementations called polyphase structures. The basic idea is to split the sum of products we need to compute for every filter output sample into multiple sub…

  • The Art of FPGA Design Season 2 - Post 11

    The Single Rate Half-Band FIR Decimator A decimating filter will reduce the sample rate of a signal, while preventing aliasing. Decimation by a factor of 2x is achieved by simply throwing out every second input sample. For this to work the input data…

  • The Art of FPGA Design Season 2 - Post 10

    The Single Rate Half-Band FIR Interpolator In the previous post we looked at the single rate half-band FIR, a particular type of odd-symmetric FIR, where almost half of the filter coefficients are zero. Not computing multiplications with these zero coefficients…

  • The Art of FPGA Design Season 2 - Post 9

    The Single Rate Half-Band FIR We have started by looking at the most general version of an FIR filter. From a mathematical point of view, this is all that is needed. There are countless variations, like the symmetric versions, both odd and even, they…

  • The Art of FPGA Design Season 2 - Post 8

    The Single Rate symmetric FIR, low latency transposed architecture The question we need to answer now is this - for those applications that require very low latency FIRs is there a way to avoid the increase in latency proportional to the filter order…

  • The Art of FPGA Design Season 2 - Post 7

    The Single Rate odd-symmetric FIR In the last post we have examined the even-symmetric FIR, a filter of order N=2*K. The main conclusion was that we only need K DSP48s to implement such a filter, and we came up with a basic building block that is both…

  • The Art of FPGA Design Season 2 - Post 6

    The Single Rate even-symmetric FIR We have looked so far at the simplest and most generic FIR possible, the single rate non-symmetric FIR filter. But many FIR filter implementations have more particular structures and taking advantage of these can improve…

  • The Art of FPGA Design Season 2 - Post 5

    The Single Rate non-symmetric FIR, direct and transpose architectures As I mentioned earlier, the single rate non-symmetric FIR filter has two possible implementations, the direct and the transpose forms. We will now apply again the retiming and pipeline…

  • The Art of FPGA Design Season 2 - Post 4

    Register pushing and the pipeline cut It should be clear by now that a direct implementation of the DSP algorithm is not good enough. Every single individual computation block, the adders and the multipliers, will require pipeline registers and there…

  • The Art of FPGA Design Season 2 - Post 3

    The basic building blocks on the FPGA implementation side The three main FPGA building blocks that are being used to implement the adders, multipliers and delays of DSP algorithms in hardware are completely different, the 6-input look up table, the flip…

  • The Art of FPGA Design Season 2 - Post 2

    The basic building blocks on the DSP algorithm side The DSP algorithms that need to be implemented are relatively simple, mathematically speaking. They consist of three basic operations, additions, multiplications and vector or matrix indexing. We will…

  • The Art of FPGA Design Season 2 - Post 1

    Crossing the gap between mathematics and physics This entire second season of The Art of FPGA Design will be about Digital Signal Processing. This is a vast subject one cannot cover in one book, let alone a few blog posts. It is a strange field which…

  • The Art of FPGA Design Season 2 - Digital Signal Processing, from Algorithm to FPGA Bitstream

    Hi, This is season 2 of the Art of FPGA Design blog. I plan to add a new post every Tuesday but depending on how long it will take me to create the content some posts could appear every other week. I have outlined below the first few posts I am planning…

  • The Art of FPGA Design - Post 35

    Sorting Networks - The results for the VHDL implementation of Batcher's sorting algorithm So how good is this VHDL implementation of a parallel sorting network? Before we look at the results here are the two modules that were missing from the previous…

  • The Art of FPGA Design - Post 34

    Sorting Networks - The VHDL implementation of Batcher's sorting algorithm OK, enough with the preliminaries, it's time now for the real deal, how do we implement in an FPGA this parallel sorting network thing . The main design goals are creating a generic…