element14 Community
element14 Community
    Register Log In
  • Site
  • Search
  • Log In Register
  • Members
    Members
    • Benefits of Membership
    • Achievement Levels
    • Members Area
    • Personal Blogs
    • Feedback and Support
    • What's New on element14
  • Learn
    Learn
    • Learning Center
    • eBooks
    • STEM Academy
    • Webinars, Training and Events
    • Learning Groups
  • Technologies
    Technologies
    • 3D Printing
    • FPGA
    • Industrial Automation
    • Internet of Things
    • Power & Energy
    • Sensors
    • Technology Groups
  • Challenges & Projects
    Challenges & Projects
    • Design Challenges
    • element14 presents
    • Project14
    • Arduino Projects
    • Raspberry Pi Projects
    • Project Groups
  • Products
    Products
    • Arduino
    • Dev Tools
    • Manufacturers
    • Raspberry Pi
    • RoadTests & Reviews
    • Avnet Boards Community
    • Product Groups
  • Store
    Store
    • Visit Your Store
    • Choose Another Store
      • Europe
      •  Austria (German)
      •  Belgium (Dutch, French)
      •  Bulgaria (Bulgarian)
      •  Czech Republic (Czech)
      •  Denmark (Danish)
      •  Estonia (Estonian)
      •  Finland (Finnish)
      •  France (French)
      •  Germany (German)
      •  Hungary (Hungarian)
      •  Ireland
      •  Israel
      •  Italy (Italian)
      •  Latvia (Latvian)
      •  
      •  Lithuania (Lithuanian)
      •  Netherlands (Dutch)
      •  Norway (Norwegian)
      •  Poland (Polish)
      •  Portugal (Portuguese)
      •  Romania (Romanian)
      •  Russia (Russian)
      •  Slovakia (Slovak)
      •  Slovenia (Slovenian)
      •  Spain (Spanish)
      •  Sweden (Swedish)
      •  Switzerland(German, French)
      •  Turkey (Turkish)
      •  United Kingdom
      • Asia Pacific
      •  Australia
      •  China
      •  Hong Kong
      •  India
      •  Korea (Korean)
      •  Malaysia
      •  New Zealand
      •  Philippines
      •  Singapore
      •  Taiwan
      •  Thailand (Thai)
      • Americas
      •  Brazil (Portuguese)
      •  Canada
      •  Mexico (Spanish)
      •  United States
      Can't find the country/region you're looking for? Visit our export site or find a local distributor.
  • Translate
  • Profile
FPGA
  • Technologies
  • More
FPGA
Blog Learning Xilinx Zynq: Interrupt ARM from FPGA fabric
  • Blog
  • Forum
  • Documents
  • Events
  • Polls
  • Files
  • Members
  • Mentions
  • Sub-Groups
  • Tags
  • More
  • Cancel
  • New
FPGA requires membership for participation - click to join
Blog Post Actions
  • Subscribe by email
  • More
  • Cancel
  • Share
  • Subscribe by email
  • More
  • Cancel
Group Actions
  • Group RSS
  • More
  • Cancel
Engagement
  • Author Author: Jan Cumps
  • Date Created: 5 Sep 2021 10:09 AM Date Created
  • Views 3299 views
  • Likes 10 likes
  • Comments 3 comments
  • summer_of_fpgas
  • zynq
  • vivado
  • summer_of_fpga
  • pynq
  • foga
Related
Recommended

Learning Xilinx Zynq: Interrupt ARM from FPGA fabric

Jan Cumps
Jan Cumps
5 Sep 2021

You can interrupt the Zynq ARM side with a signal coming out of the FPGA part of the chip. In this post, I test this.

The FPGA part has a few blocks that will generate interrupts. In a Jupyter notebook, I'll try to show that they are detected by the processors and OS.

 

In this article, I try out an approach discussed on the Pynq forum. It doesn't use VHDL or Verilog.

The interrupts are generated from 2 Xilinx Timer IP blocks.

But they could as well be generated from your own IP (E.g.: you could generate it from one of the pins of the Johnson Counter used in a previous post).

 

Block Design

 

image

image: block design. Green blocks generate interrupts in the fabric. Red blocks are helpers to collect and format to a signal that's understood by the ARM/Linux part.

 

The processing system, reset and interconnect blocks are wired up as usual.

The design uses 3 masters in the interconnect. Two are used as interface with the 2 timers. The 3rd master talks to the interrupt controller.

These blocks will be addressable from Linux - in this case a Jupyter notebook.

 

There are boundaries when doing this on a system that runs stock Linux images for the Pynq ecosystem.

I take these into account in this design.

In the version of Pynq that I'm using (2.6), there is a practical issue: the interrupt fires twice from FPGA before the Python code in the Jupyter notebook resets it. This makes that every other time the code returns immediately after priming the interrupt. It's acknowledged by Pynq designers (see my comment in the Pynq forum thread I linked at the start of this frame.

 

Update 1: See the comments below. There is a solution.

Update 2: the solution works, and I have amended this post.

 

Two timers will generate interrupts. They are managed by an interrupt controller.

image

The purple rectangle shows the solution to an issue I had when I initially wrote this post.

The interrupt would fire twice, interfering with every other time a Pynq function was using it.

See: https://discuss.pynq.io/t/zynq-ps7-interrupts/198/10

 

 

The processor system is configured to accept interrupts

image

Not shown, but input for the interrupt controller: processor clock is 650 MHz (fixed on my board), fabric clock 0 is set to 100 MHz (configured for this project..

 

In the remainder of this post, I will hide the clock and reset lines.

I've shown them in overview image at the top of this post. You can also see them if you download the attached Vivado project.

It helps to focus on the design specific functionality:

image

Here's the regenerated "simplified" layout compared to the block design with all signals shown:

 

image image

 

Catching the interrupts in the ARM/Linux part

 

When the bitstream of this design is loaded in the Zynq, there should be interrupts arriving each time one of the timers fires one.

In the spirit of the Pynq ecosystem, a Jupyter notebook is used to make this visible.

The notebook will execute a loop, that will be interrupted when the trigger of timer 1 fires.

 

image

image: interrupt path through fabric

 

Steps:

  • register and configure the timer
  • define an interrupt handler wait_for_timer1()
  • create an event loop and have it interrupted by the handler.

 

image

This is the exact code of the Pynq forum thread I referred to above.

The exercise is successful if the last block of the notebook doesn't spin indefinitely, but completes.

You can see that if the annotation in the front of the block changes from [*] to [a number].

 

Vivado project (2020.2) and Jupyter notebook attached.

 

Pynq - Zync - Vivado series
Add Pynq-Z2 board to Vivado
Learning Xilinx Zynq: port a Spartan 6 PWM example to Pynq
Learning Xilinx Zynq: use AXI with a VHDL example in Pynq
VHDL PWM generator with dead time: the design
Learning Xilinx Zynq: use AXI and MMIO with a VHDL example in Pynq
Learning Xilinx Zynq: port Rotary Decoder from Spartan 6 to Vivado and PYNQ
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control
Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ
Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations
Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency
Learning Xilinx Zynq: Hardware Accelerated Software
Automate Repeatable Steps in Vivado
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design
Learning Xilinx Zynq: Logic Gates in Vivado
Learning Xilinx Zynq: Interrupt ARM from FPGA fabric
Learning Xilinx Zynq: reuse and combine components to build a multiplexer
PYNQ version 2.7 (Austin) is released
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors
Use the ZYNQ XADC with DMA part 1: bare metal
Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse

 

Attachments:
interrupt.zip
interrupt_jupyter.zip
  • Sign in to reply
  • Jan Cumps
    Jan Cumps over 1 year ago in reply to Jan Cumps

    I had submitted a pull request to the Pynq repository to adapt the example's documentation.

    That got approved and will be part of release 2.7. First little contribution to the community.

    This wll very likely not be the final solution. The team is thinking about introducing a callback that allows to clear interrupts.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • More
    • Cancel
  • Jan Cumps
    Jan Cumps over 1 year ago

    Works! The interrupt now nicely waits the correct time, each time.

    Communities for the win. It was resolved by another Pynq user.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • More
    • Cancel
  • Jan Cumps
    Jan Cumps over 1 year ago

    In the post, I reported this issue:

    In the version of Pynq that I'm using (2.6), there is a practical issue: the interrupt fires twice from FPGA before the Python code in the Jupyter notebook resets it.

    I logged this on the Pynq support forum and got several replies.

    There's a possible solution:

    https://discuss.pynq.io/t/zynq-ps7-interrupts/198/10

    I'm testing that now ...

     

    image

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • More
    • Cancel
element14 Community

element14 is the first online community specifically for engineers. Connect with your peers and get expert answers to your questions.

  • Members
  • Learn
  • Technologies
  • Challenges & Projects
  • Products
  • Store
  • About Us
  • Feedback & Support
  • FAQs
  • Terms of Use
  • Privacy Policy
  • Legal and Copyright Notices
  • Sitemap
  • Cookies

An Avnet Company © 2023 Premier Farnell Limited. All Rights Reserved.

Premier Farnell Ltd, registered in England and Wales (no 00876412), registered office: Farnell House, Forge Lane, Leeds LS12 2NE.

ICP 备案号 10220084.

Follow element14

  • Facebook
  • Twitter
  • linkedin
  • YouTube