In my previous blog, I showed how I installed Vivado & Vitis 2023.1 on my Ubuntu 22.04 LTS PC. This will be my first hands-on experiment using the MiniZed board and Vivado. I will turn ON/OFF an LED using a switch that is pre-built into the MiniZ...
This is my third blog post in a series that cover my experience going through the training courses of the Path to Programmable 3 challenge. The first two blog posts, Blog1 and Blog2, have covered the beginning of participating in this challenge...
What is Path to Programmable 3
An initiative program from Element14 to encourage the FPGA Enthusiast to offer structured FPGA-based SoC training.
Encourages the challengers to Submit an idea of implementation.
A Expert committee fro...
Exploring Ultra96-V2 Linux terminal over SSH
Some questions about terminal emulators
What are terminal emulators ?
A terminal emulator, or terminal application, is a computer program that emulates a video terminal&n...
Introduction:
The Ultra96-V2 comes with a lot of good pre-built, out-of-box demo material from Avnet to get started quickly. However, the real power of FPGAs is in being able to build custom hardware. In the case of Zynq Ultrascale, which this b...
Start a Zynq MPSoC Design
Table of Contents
1 Creating New FPGA design
2 Create FPGA design with VIVADO
3 Create block design
4 Build the Design
5 Summary
1 Creating New FPGA design
The design and application of FPGA are highly flexib...
Table of Contents
The Hardware Lab
Windows troubleshooting
Captures
The Hardware Lab
You may recognize the diagram above, don't you? The diagram corresponds to the Lab 8 in the Hardware manual. Directly from it, I had to do some small chang...
Table of Contents
Introduction
What's all this platform?
Using printf(), xil_printf(), XUartPs_Send()
Using the PWM module
The application
Tutorial queries
Introduction
Path to Programmable III is an interesting contest and with t...
Introduction
The AvnetMinized development board has as its sound sensor an ST MP45DT02 MEMS microphone that generates a 1-bit pulse density modulated (PDM) signal. In this blog we are going to see different alternatives to conve...
This is my second blog post in a series that cover my experience going through the training courses of the Path to Programmable 3 challenge. The first blog post, has covered the beginning of participating in this challenge and my learning expe...
This is my first blog in the Path to Programmable III Contest. This is going to be my first big journey toward the FPGA world. I have a master's degree in electrical & electronic engineering but I never practically worked with FPGA seriously....
The Avnet Minized board only exposes 4 channels of the integrated analog-to-digital converter (XADC). How can we do to read more analog channels on the AvnetMinized? There is a solution using an external multiplexer and that is what I am going ...
Here I am with my first blog post for the Path to Programmable III challenge. First, I would like to thank Element 14 for selecting me to be part of this design challenge.
I am looking forward to exploring the training materials and to b...
Introduction of Ultra 96 v2 kit
The Ultra 96 v2 is Arm-based, Xilinx Zynq UltraScale+ MPSoC development board based on the Linaro 96 Boards Consumer Edition Specification. The kit contains certified radio module from Microchip. All components o...
Table of Contents
Objectives
Build BRAM + PWM IP Vivado Project
Petalinux Project For Lab 7
Boot Petalinux from JTAG
References
Objectives
As my Blog #2 said, the MiniZed is a single ARM Cortex®-A9 processor APU FPGA device. That mean...
Install Software and Petalinux
Table of Contents
1 Install Software and Petalinux
2 Install Vitis and Vivado
3 Install Petalinux in Windows 10 WSL 2 or Bare Unbuntu 22
4 Next
1&n...
Table of Contents
Introduction
BRAM Structure
BRAM Controller Structure
MiniZed TTC Lab5 and Lab6 Report
Introduction
The MiniZed is a single ARM Cortex®-A9 processor mated with 28nm Artix 7 based programmable logic, representing a low ...
Introduction
In the current exercise, I want to evaluate the portability and reusability features provided by the Vitis Unified Software Platform environment to migrate an application I developed with a Spartan-7 FPGA, implementing a MicroBlaze soft ...
Path to Programmable III Intro
This is the first blog of my participation in the element14 Path to Programmable III program.I have chosen the MiniZed development board for my participation. I have never worked with Zynq processors before a...
Project Phases
Dates
Application Period
31st March 2023
Application Deadline
14th May 2023
Participants Announced
17th May 2023
Training Begins
26th May 2023
Training Ends
26th July 2023
Training Blogs for Credit Due
27th July 2023
...
Ultra96-V2 Kits Unboxing
Table of Contents
1 Training
2 Kits
3 Plans to do
1 Ultra96 Training Courses
The Path to Programmable III training courses is exploration to new realm of developing Zynq Ultrascale+ MPSoC hardwa...
