Hardware Training Summary
Lesson 4: Peripherals
Zynq MPSoC General connectivity
PS IO : MIO only
Qual SPI
NAND
GEM - Gigabit Ethernet
USB2.0 through ULPI interface
GPIO : 0-2 Bank
EMIO/EMIO Possibility
SD/SDIO/eMMC
Control Area ...
This is my Fourth training blog as part of the Path to Programmable 3 design challenge. As mentioned in the First Blog, this blog will be focussed on Vitis. I will give an overview about Vitis, its features. Then we will be using the ...
Table of Contents
PYNQ
Computer Vision
An example
Conclusion
PYNQ
According to webpage, PYNQ is an open-source project from AMD that makes it easier to use Adaptive Computing platforms. Nowadays, there are support for a wide variety of boards; am...
What is Vivado
IDE to Synthesize and Analysis of HDL/Verilog Language
A single tool to Write, Compile, Simulate and Program
Hardware Training Summary
Lesson 2: The Case for a System-on-Chip
Case for SoC : Why do we need SoC
...
In the Second Blog, I mentioned how to create a minimalistic hardware design based on Vivado. As mentioned in the First Blog, This blog post will be focussed on Petalinux. I will use the .xsa file from the minimalistic hardware design generated in th...
Hello everyone, I am very excited to start my blog series with Minized Board unboxing and general overview.
Unboxing:
Alright, here's the Minized board and it arrived in a neatly packaged box. The box features a sleek design. Inside the box, we...
Table of Contents
Objectives
Background Knowledge about Petalinux Drivers
Build Simple User APIs for Petalinux Project
Conclusions
Objectives
I continued to use Lab 7 Vivado project to build a couple of simple user APIs under Petalinux e...
As mentioned in the First Blog, this blog will be focussed on Vivado based HW design. I will be writing about my experience in creating a simplest/minimalistic hardware design with the least amount of peripherals that is sufficient to do a SD c...
Table of Contents
Introduction
1G Ethernet
Gigabit Transceiver (GTX/GTH)
JESD Standard
References
Introduction
Moving on with the exploration of FPGAs, I stumbled upon this question of what really can FPGAs can do and where they fit in - unl...
This is my fifth blog post in a series that covers my experience going through the training courses of the Path to Programmable 3 challenge. The first four blog posts, Blog1, Blog2, Blog3, and Blog4, have covered the beginning of part...
I am very grateful to element14 for giving the opportunity to participate in the Path to Programmable 3 design contest. I will be participating in the ultra96v2 track. I might be a bit late to join the party, but I have a lot of (exciting) things to ...
Xilinx ZYNQ-7000 AP SoC consists of a Programmable Logic (PL)(FPGA) and Processing Subsystem(PS) (ARM Cortex-A9). The communication logic/interface between the PL and PS is an essential component of ZYNQ Architecture for data transfer. The AXI Interc...
The Vivado Design Suite provides an IP-centric design flow that helps us quickly turn designs and algorithms into reusable IPs. The Vivado IP catalog is a unified IP repository that provides the framework for the IP-centric design flow. This catalog ...
My initial idea for the last training blog on the "Path to Programmable 3" challenge was to dedicate it to write about my experiences tinkering with the WIFI and Bluetooth communication of the MiniZed dev board. The road soon went wrong.
There a...
AMD Vitis unified software platform
Some question with respect to AMD vitis unified development platform
What is AMD Vitis unified development platform ?
The Vitis unified software platform is an integrated development environment (IDE) for the...
Table of Contents
The MAX7219 Peripheral
The Software
Result
The MAX7219 Peripheral
The MAX7219 IC is a "Serially Interfaced 8-Digit LED Display Driver", which interface is based on SPI, with an specific protocol for configuration and data manage...
Introduction
In this blog post I want to touch a more operational topic related to working with AMD FPGAs. I have been working with AMD FPGAs for some time and this blog post is inspired by an issue I have faced several times in the past
When debuggi...
Welcome to my first blog on the Path Programmable III contest. Since other challengers had made awesome blogs on how to set up the IDE & troubleshoot, I'll be writing about my journey in making a Bottle Cap Inspection experiment with the Xil...
Exploring Vivado IDE to build the hardware design
Some questions about VIVADO
What is vivado ?
Vivado is a highly complex integrated development environment (IDE) tool for the entire FPGA design and implementation process.
What is HDL...
What is Zynq
The Zynq architecture, as the latest generation of Xilix’s all-programmable System-on-Chip (SoC) families, combines a dual-core or single-core ARM Cortex-A9 with a traditional (FPGA). The interface between the different elements wi...
Software Application Development with Vitis
Table of Contents
1 Software Application Development
2 Import hardware design file
3 Update the BSP
4 Create application
5 Program the hardware
1 Software Application Development
After design hardware ...
Table of Contents
Wiring the platform
The firmware
The result
Wiring the platform
This time, I am using the content of the Software manuals. According to the learning curve, we have a pre-defined architecture in the design_1_wrapper.xsa with a lo...
I received the kit for the Path to Programmable 3 rather quickly compared with other kits I received for RoadTesting. Usually, it took several days until I could get the kit in my hand, and several emails needed to be exchanged with the customs offic...
This is my fourth blog post in a series that cover my experience going through the training courses of the Path to Programmable 3 challenge. The first three blog posts, Blog1, Blog2, and Blog3, have covered the beginning of participating in thi...
