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Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

Jan Cumps

made a Software Defined Radio (SDR) Experiment Board. One of the components is a digital quadrature oscillator.

It's a circuit with 4 PWM outputs that are each 90° shifted.

In Shabaz' blog, the oscillator is made with flip-flops, and controlled by an external function generator.

Because it's the Summer of FPGAs, I'm proposing 2 FPGA based alternatives.

They work identical, generate the same frequency (input / 4), but the approach is different.

One works by replaying a predefined output pattern on the 4 outputs, with one clock delay for each output.

The second one by calculating the first channel based on a counter value, and left shifting the data through the outputs.

 

The entity is identical for the two approaches:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity quadrature_oscillator is
  Port (
    i_clk: in std_logic;
    i_nReset: in std_logic;
    o_outputs: out std_logic_vector (3 downto 0)
   );
end quadrature_oscillator;

 

This is the first implementation.

The pattern used to define the outputs is 0011001.

Each of the pins continuously cycles through a (different!) range of 4 bits of the pattern, on the cadence of the clock.

pin 0 from 3 to 6: 1100

pin 1 from 2 to 5: 0110

pin 2 from 1 to 4: 0011

pin 3 from 0 to 3: 1001

They do this at the same time, in parallel.

You can see that this generates an output where each of the pins is 90° shifted.

 

architecture Behavioral of quadrature_oscillator is
  signal s_pattern: std_logic_vector (6 downto 0) := "0011001";
  signal s_counter: natural range 0 to 3 := 0;

begin
process (i_clk, i_nReset)
begin
--  if i_nReset = '0' then
--    s_counter <= 0;
--  els
  if rising_edge(i_clk) then
    if s_counter = 3 then
      s_counter <= 0;
    else
      s_counter <= s_counter + 1;
    end if;
    o_outputs(0) <= s_pattern(s_counter + 3);
    o_outputs(1) <= s_pattern(s_counter + 2);
    o_outputs(2) <= s_pattern(s_counter + 1);
    o_outputs(3) <= s_pattern(s_counter);
  end if;
end process;

end Behavioral;

 

The second implementation takes a different approach.

The data is the output vector is shifted 1 position to the left. That generates 90° phase shift.

I only have to take care that I set the LSB correct each time. For that, I use the MSB of the counter, inversed.

The counter is 2 bits. It cycles 00 -> 01 -> 10 -> 11.

If you take the MSB each time, inversed, you get 1100.

That's the identical as the output of pin 0 in the first implementation. The left-shift does the rest of the magic for the other 3 pins.

 

architecture Behavioral of quadrature_oscillator is
  signal s_counter: UNSIGNED (1 downto 0) := "00";
  signal s_buffer: std_logic_vector (3 downto 0) := (others => '0');

begin
process (i_clk, i_nReset)
begin
  if i_nReset = '0' then
    s_counter <= "00";
    s_buffer <= (others => '0');
  elsif rising_edge(i_clk) then
    if s_counter = "11" then 
      s_counter <= (others => '0');
    else
      s_counter <= (s_counter) + 1;
    end if;
    s_buffer <= s_buffer (2 downto 0) & not(s_counter(1));
    o_outputs <= s_buffer;
  end if;
end process;

end Behavioral;

 

I've attached Vivado project and Jupyter notebook. Implementation #2 is active, approach #1 is commented out.

The VHDL for #2 is adapted, see https://www.element14.com/community/groups/fpga-group/blog/2021/08/04/learning-xilinx-zynq-a-quadrature-oscillator#comme… .

Latest source on github: https://gist.github.com/jancumps/0a1b2692ddfd6edc79e8487adc66539e

 

Which design do you prefer? Or do you have an alternative?

 

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Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency
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PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
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Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse

 

Attachments:
quad_osc_jupyter.zip
quadrature_oscillator.zip
Anonymous

Top Comments

  • in reply to Jan Cumps

    It works.

     

     

    With a clock of 100 MHz, and an 8 bit divider, I have between 48.8284 KHz and 12.5001 MHz.

    First step approx. 371 Hz, last one 6.25 MHz.

     

    There are many VHDL runtime configurable clock dividers available online. I've written one myself for this exercise:

     

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity variable_clock is
    Port ( 
      clk_i    : in  STD_LOGIC;
      resetn_i : in  STD_LOGIC;
      ticks_i  : in  STD_LOGIC_VECTOR (7 downto 0);
      clk_o    : out STD_LOGIC
    );
end variable_clock;

architecture Behavioral of variable_clock is
  signal s_counter: natural range 0 to 2**ticks_i'length-1 := 0;
  signal s_clk_out: STD_LOGIC := '0';
begin

process (clk_i, resetn_i)
begin
  if resetn_i = '0' then
    s_counter <= 0;
    s_clk_out <= '0';
  elsif rising_edge(clk_i) then
    if s_counter >= unsigned(ticks_i) then -- >= because the value can change
      s_counter <= 0;
      s_clk_out <= not s_clk_out;
    else
      s_counter <= s_counter + 1;
    end if;
    clk_o <= s_clk_out;
  end if;
end process;

end Behavioral;

  • While I'm building up Shabaz' SDR, I'm refining the FPGA quadrature oscillator.

    I'd like to make its frequency change in steps. Programmable from the Zynq ARM/Linux PS.

     

    To prevent that I have to alter the quadrature oscillator VHDL, I'm adding a clock changer at the input of its clock input.

    At this moment a naive one. A clock divider.

     

     

    The output frequency of the quadrature oscillator is always its input frequency / 8.

    So if I divide the input clock by 2, the effective frequency is input / 16.

  • in reply to shabaz

    impressive to hear that the FPGA clock capabilities can at least resolve down to 60 kHz ballpark

     

    Yes, but it's not neat and tidy like it would be if the PD was down at the channel spacing value and the outputs were all simple multiples of that, like a frequency synthesizer would do it.

     

    Here I was looking at varying the divider down from the input clock to the PD, the divider down from the VCO output to the PD, and the divider down from the VCO for the output. It's all sorts of odd values coming out. Here it is as a partial table.

     

     

    The 48MHz I've divided by 8 to give 6MHz [above the PD min], then the VCO is about 200 times that, so 1.2GHz [less than the max of 1300MHz], and an output divide of around 100 to place the resulting frequency near 12MHz [an arbitrary choice of tuning frequency]. The rounded figures show a rough 60k granularity to the result.

     

    To be fair to Altera/Intel, they haven't designed the PLL to do this and be used in a general way for telecoms and clock recovery.

     

    I guess external loop filter+VCO could be used

    According to the datasheet, a 74LV4046 can get to 38MHz. [Aside: the 74LV4066 is a good bit faster than the HC one, too]. That isn't enough for 4x HF band, but I wondered if one could then simply perch the FPGA PLL on top to generate the 4 phases [or, alternatively, multiply it by 4 and use one of these logic schemes].

  • in reply to shabaz

    With the vhdl code version, you can go from Hz to MHz.

  • in reply to jc2048

    I see.. I guess external loop filter+VCO ould be used, but then that's becoming a major project in itself. Still, impressive to hear that the FPGA clock capabilities can at least resolve down to 60 kHz ballpark, that's useful to know for other projects too, and where the ADC sample rate allows for more than that bandwidth.