Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations

It works.

With a clock of 100 MHz, and an 8 bit divider, I have between 48.8284 KHz and 12.5001 MHz.

First step approx. 371 Hz, last one 6.25 MHz.

There are many VHDL runtime configurable clock dividers available online. I've written one myself for this exercise:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity variable_clock is
    Port ( 
      clk_i    : in  STD_LOGIC;
      resetn_i : in  STD_LOGIC;
      ticks_i  : in  STD_LOGIC_VECTOR (7 downto 0);
      clk_o    : out STD_LOGIC
    );
end variable_clock;

architecture Behavioral of variable_clock is
  signal s_counter: natural range 0 to 2**ticks_i'length-1 := 0;
  signal s_clk_out: STD_LOGIC := '0';
begin

process (clk_i, resetn_i)
begin
  if resetn_i = '0' then
    s_counter <= 0;
    s_clk_out <= '0';
  elsif rising_edge(clk_i) then
    if s_counter >= unsigned(ticks_i) then -- >= because the value can change
      s_counter <= 0;
      s_clk_out <= not s_clk_out;
    else
      s_counter <= s_counter + 1;
    end if;
    clk_o <= s_clk_out;
  end if;
end process;

end Behavioral;

While I'm building up Shabaz' SDR, I'm refining the FPGA quadrature oscillator.

I'd like to make its frequency change in steps. Programmable from the Zynq ARM/Linux PS.

To prevent that I have to alter the quadrature oscillator VHDL, I'm adding a clock changer at the input of its clock input.

At this moment a naive one. A clock divider.

The output frequency of the quadrature oscillator is always its input frequency / 8.

So if I divide the input clock by 2, the effective frequency is input / 16.

impressive to hear that the FPGA clock capabilities can at least resolve down to 60 kHz ballpark

Yes, but it's not neat and tidy like it would be if the PD was down at the channel spacing value and the outputs were all simple multiples of that, like a frequency synthesizer would do it.

Here I was looking at varying the divider down from the input clock to the PD, the divider down from the VCO output to the PD, and the divider down from the VCO for the output. It's all sorts of odd values coming out. Here it is as a partial table.

The 48MHz I've divided by 8 to give 6MHz [above the PD min], then the VCO is about 200 times that, so 1.2GHz [less than the max of 1300MHz], and an output divide of around 100 to place the resulting frequency near 12MHz [an arbitrary choice of tuning frequency]. The rounded figures show a rough 60k granularity to the result.

To be fair to Altera/Intel, they haven't designed the PLL to do this and be used in a general way for telecoms and clock recovery.

I guess external loop filter+VCO could be used

According to the datasheet, a 74LV4046 can get to 38MHz. [Aside: the 74LV4066 is a good bit faster than the HC one, too]. That isn't enough for 4x HF band, but I wondered if one could then simply perch the FPGA PLL on top to generate the 4 phases [or, alternatively, multiply it by 4 and use one of these logic schemes].

With the vhdl code version, you can go from Hz to MHz.

I see.. I guess external loop filter+VCO ould be used, but then that's becoming a major project in itself. Still, impressive to hear that the FPGA clock capabilities can at least resolve down to 60 kHz ballpark, that's useful to know for other projects too, and where the ADC sample rate allows for more than that bandwidth.