The main target for Zynq family FPGAs is: compute systems with hardware acceleration.

It's architecture focuses on being able to stream data efficiently between ARM and FPGA submodules.

The FPGA can then perform manipulations in hardware that take too long in software.

The tool chain supports this. The Vitis HLS IDE's only goal is to convert C functions to FPGA IPs..

I have edited this article for Vivado and Vitis HLS version 2020.2.

The examples are updated for these versions, and work with Pynq 2.6 and 2.7.

You get the working sources right now via git clone -b image_v2.7_2020.2 https://github.com/mariodruiz/PYNQ-HelloWorld.git --recursive.

A merge request is open to het it into the Xilinx repo https://github.com/Xilinx/PYNQ-HelloWorld/tree/image_v2.7.

Hardware Accelerated Image Resize Algorithm

As proof of concept,  Xilinx adapted OpenCV so that you can build functions and filters in hardware.

I'm reviewing such an example: image resize.

This demo performs the same exercise twice: resize an image from 3840 * 2160 to  1920 * 1080

• using the ARM processor to execute OpenCV resize calls
• using the same function, implemented inside the FPGA fabric.

The results:

in software, it took 1.03 s. In hardware, 210 ms.

The test is both times done in a loop, taking the fastest execution as benchmark. This to take in account optimising, caching, incidental OS activity, ...

The time taken is from having the original image in memory,  to when the algorithm has finished writing the resized image to memory.

Resize executed in ARM processors	Resize executed in FPGA fabric

The Accelerated Resize Function Design

This is done in Vitis HLS. The example uses the Xilinx OpenCV port and calls its resize() function.

The C code (full):

void resize_accel(stream_t& src, stream_t& dst,
                  int src_rows, int src_cols,
                  int dst_rows, int dst_cols) {
    // Convert stream to xf::cv::Mat
    axis2xfMat<DATA_WIDTH, TYPE, HEIGHT, WIDTH, NPIX>(src, src_mat);
    // Run xfOpenCV kernel:
    xf::cv::resize<INTERPOLATION, TYPE, HEIGHT, WIDTH, HEIGHT, WIDTH, NPIX, MAXDOWNSCALE>(src_mat, dst_mat);
    // Convert xf::cv::Mat to stream
    xfMat2axis<DATA_WIDTH, TYPE, HEIGHT, WIDTH, NPIX>(dst_mat, dst);
    
}

Vitis HLS converts this into an FPGA IP (both Verilog and VHDL source are generated).

This IP can then be used in Vivado

The Accelerated Resize Function Used

You can use this generated IP similar to other IPs in Vivado. In the image below, it's the orange block.

Inputs and outputs are interfaced with the ARM controllers via the AXI interface.

Install on Pynq Board

This is straightforward.

You open a Linux terminal. There is one available from the Jupyter home page of your board. Or you can use PuTTY, etc.

Then follow the Quick Start. The two notebooks with ARM and FPGA implementations will become available