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  • Author Author: Jan Cumps
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Automate Repeatable Steps in Vivado

Jan Cumps

Life hack to automate the creation of a project in Vivado.

 

video source: real time capture of script execution on my laptop

 

Many projects have repeatable steps at the setup stage. This script helps to automate this. It creates a new project with your typical starting blocks.

Before calling the script, close the currect project, if one is open.

If you just opened Vivado, you are good to go. The Tcl prompt is at the bottom of the startup screen.

Set these two properties using that prompt. The Vivado project will be created with that name and location you define here.

 

set projectname myProject
set projectroot D:/users/jancu/Documents/elektronica/xilinx/zynq/prj

 

TCL script:

gist: https://gist.github.com/jancumps/a10e0395fe37c70e8d90fdba1ebae948#file-create_project-tcl

 

create_project $projectname $projectroot/$projectname -part xc7z020clg400-1
set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project]
set_property target_language VHDL [current_project]

create_bd_design "design_1"
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
endgroup
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0
endgroup
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
endgroup
startgroup
set_property -dict [list CONFIG.NUM_MI {1}] [get_bd_cells axi_interconnect_0]
endgroup
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
connect_bd_net [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins proc_sys_reset_0/ext_reset_in]
connect_bd_net [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_interconnect_0/ARESETN]
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN]
connect_bd_net [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_gpio_0/S_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/M_AXI_GP0] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
save_bd_design

 

image

image source: screen capture of the block design after the script finished

 

The script

  • sets the correct device (for my Pynq-Z2. If you have another board, create one project manually and harvest the steps from the Tcl log)
  • creates a project and a block design
  • adds the Zynq PS and applies board presets
  • adds reset and AXI IPs
  • connects and saves.
  • is tested with Vivado 2020.2, but doesn't use version specific constructs.

voila.

 

 

Pynq - Zync - Vivado series
Add Pynq-Z2 board to Vivado
Learning Xilinx Zynq: port a Spartan 6 PWM example to Pynq
Learning Xilinx Zynq: use AXI with a VHDL example in Pynq
VHDL PWM generator with dead time: the design
Learning Xilinx Zynq: use AXI and MMIO with a VHDL example in Pynq
Learning Xilinx Zynq: port Rotary Decoder from Spartan 6 to Vivado and PYNQ
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control
Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ
Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations
Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency
Learning Xilinx Zynq: Hardware Accelerated Software
Automate Repeatable Steps in Vivado
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design
Learning Xilinx Zynq: Logic Gates in Vivado
Learning Xilinx Zynq: Interrupt ARM from FPGA fabric
Learning Xilinx Zynq: reuse and combine components to build a multiplexer
PYNQ version 2.7 (Austin) is released
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors
Use the ZYNQ XADC with DMA part 1: bare metal
Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse

  • when you want to execute a tcl script file from the prompt, the command is source.

     

    source d:/tcl_scripts/create_project.tcl

  • some random commands I've used recently, to visualise selected objects for blogs:

     

    highlight_objects -color blue [get_bd_cells /timer_0]
highlight_objects -color blue [get_bd_cells /timer_*]
highlight_objects -color blue [get_bd_cells /processing_system7_0]
highlight_objects -rgb {255 0 0} [get_bd_cells /timer_*]
mark_objects [get_bd_cells /timer_*]
mark_objects [get_bd_cells /*axi*]
unmark_objects [get_bd_cells /timer_*]
unhighlight_objects
unmark_objects

  • in reply to Jan Cumps

      wrote:

    I wrote one before by hand, to collect and rename the .hwh and .bit files of a project for use on a Pynq board and Jupyter notebook.

     

    here it is:

    (also available on GitHub)

     

    set project_path [get_property directory [current_project]]
set project_file [file rootname $project_path]
set __project [current_project]
set hw_dir [file dirname [get_files *.hwh]]
set hwhandoff [glob [file join $hw_dir *.hwh]]
set bitstream [glob [file join $project_path $__project.runs impl_1 *.bit]]

#gather in the prj directory
file copy -force $hwhandoff $project_file.hwh
file copy -force $bitstream $project_file.bit

     

    Works from the currently open project, after a successful bitstream generation.

    It will place the .hwh and .bit file in the directory above the current project's directory. Both have the same file base name, as expected by Pynq.

    Based on https://forums.xilinx.com/t5/Welcome-Join/How-do-I-change-the-location-of-the-bitstream-file-in-Vivado/td-p/737489, tested in Vivado 2020.2.

     

    If you run this from the Vivado TCL Shell, open the project first, before running the script.

    Example:

    cd d:/users/jancu/documents/elektronica/xilinx/zynq/prj/quad_pwm
open_project -quiet quad_pwm

  • in reply to Andrew J

      wrote:

     

    ... the TCL console shows the actual commands being executed as you 'do stuff' in Vivado.  ...

    That is how I captured the commands for this article. I played the creation of a project in the GUI and grabbed the TCL commands.

     

    I wrote one before by hand, to collect and rename the .hwh and .bit files of a project for use on a Pynq board and Jupyter notebook.

    When you're developing iteratively and incremental, you will find yourself collecting these files from different directories, then rename them, often. Automation helps there too.

  • Great work! Thank you for showcasing this. Avnet's more advanced projects take advantage of Tcl scripting, so it is well worth the time to understand Vivado Tcl capabilities. If you want to see some of Avnet's examples, this blog by will share where to find Avnet's scripts on GitHub.

    Avnet HDL git HOWTO (Vivado 2020.2 and later)

     

    Bryan