Build a big multiplexer by reusing small multiplexers.
FPGA designs are (re)usable as components. In this post I'm showing that you can make a 4-input multiplexer by combining several 2-input multiplexers.
A 2-input multiplexer is a simple digital building block. The 4-input multiplexer shown here is made out of 3 of these 2-input blocks.
A multiplexer is a device that allows you to select one input and send that to the output.
You can compare it to the source selector of your stereo system, where you can switch inputs between radio, CD player, ...
In this case, we have 4 digital inputs. There will always be one of them connected to the output. The rest is ignored.
This circuit is used a lot. You'll find it in microcontrollers where you can choose the function of the pins. A pin can be a GPIO, an I2C clock in, a SPI chip select, a timer, ...
In this post, I'll use the 4 buttons on my Pynq board as inputs, and an LED as output.
A register (It's a Zynq device, so I like to combine ARM and FPGA) will define what input is multiplexed to the output, and thus drives the LED state.
The VHDL is 100% from ALL ABOUT FPGA. Check it out, because they also show a single-block 4-input multiplexer.
image source: shabaz' post Building an RF Switching Unit
I am deliberately no diving into the VHDL details in this post. ALL ABOUT FPGA cover it, including simulation.
I'm trying to fair-use them, without stealing sunshine.
1: I'm using a software controlled register (a memory location that's shared between the Zynq ARM and Zynq FPGA) to select the input. But in essence, that input selector is just a two bit input. You don't need the ARM and the Zynq. It can be controlled by simple FPGA pins.
2: The goal of this post is to show how you can use and reuse designs. Not to build the best multiplexer. I selected a multiplexer because it's a great simple example.
3: comment if this post isn't clear. I'm trying to combine both FPGA design (main goal) and the Zynq/Pynq environments. 2 Different technologies that help me to learn FPGA design faster. But it may blur the pure FPGA part. If it does, inform me.
My design uses the 4 buttons of my development board as inputs.
The output is one of the LEDS.
At any time, the LED will show the status of exactly one of the 4 buttons. Real time.
Only one of the 4 buttons can control the LED at a given time. The multiplexer (mux) will decide what button will do that.
When you start up, the first button will turn the led on and off.
The mux will allow you to select one of the other 3 buttons.
The 2-input -> 1-output mux is written in VHDL. The 4-input -> 1-output mux is then based on the 2-input design. It's also written in VHDL.
You can find the source here: 4 to 1 Mux Implementation using 2 to 1 Mux.
entity mux2_1 is Port ( a_in, b_in : in STD_LOGIC; s_in : in STD_LOGIC; z_out : out STD_LOGIC); end mux2_1; architecture Behavioral of mux2_1 is begin -- see https://allaboutfpga.com/vhdl-4-to-1-mux-multiplexer/ end Behavioral; entity mux4_1 is Port( a_in, b_in, c_in, d_in : in STD_LOGIC; s0_in, s1_in : in STD_LOGIC; z_out : out STD_LOGIC); end mux4_1; architecture Behavioral of mux4_1 is component mux2_1 port( a_in, b_in : in STD_LOGIC; s_in : in STD_LOGIC; z_out : out STD_LOGIC); end component; signal temp1, temp2 : std_logic; begin m1: mux2_1 port map(a_in => a_in, b_in => b_in, s_in => s0_in, z_out => temp1); m2: mux2_1 port map(a_in => c_in, b_in => d_in, s_in => s0_in, z_out => temp2); m3: mux2_1 port map(a_in => temp1, b_in => temp2, s_in => s1_in, z_out => z_out); end Behavioral;
Multiplexer in the Vivado block design
The two inputs and the output are made external in the block design.
mux_in is a vector that represents the inputs a, b, c, d. You'll see later that it's connected to the 4 buttons.
sel_in is the 2 bit register that decides which input will be connected to the output. It's going to be mapped to an ARM/Linux memory address.
mux_out is the output z that will go to an LED.
Check the ALL ABOUT FPGA pages for the truth table.
I'm using the ARM/Linux part of the Zynq to select what input is active. A 2 bit AXI register controls the multiplexer.
image: the selection of the multiplexer is controlled by the ARM.
The 4 buttons are tied to the mux inputs (D19, D20, L20, L19), an LED to the mux output (R14).
image: constraints that bind the FPGA pins to the buttons and LED
Test from Pynq
The multiplexer is tested in Pynq, with a jupyter notebook.
The first 3 cells load the Vivado FPGA bitstream, and prepare the variable that represents the multiplexer selection register
image: jupyter notebook allows to select input a, b, c or d by writing to the mux register
Then the 4 possible states of the register are defined, and it's put to the test:
This call links (multiplexes) button BTN3 to the LED LD0
image: the multiplexer in action. Input d is selected.