Learning Xilinx Zynq: Logic Gates in Vivado

Jan Cumps

18 Aug 2021

When you're working on a Vivado Block design, you can add IP.

There are 100s of options available. But you will not find a NOT gate, AND gate, ...

They are there though, available under the cryptical name Utility Vector Logic and Utility Reduced Logic

Utility Vector Logic:

Works on vector inputs, and outputs a vector where the logic has been applied to each of the bits.

There is AND, OR, XOR and NOT

Utility Reduced Logic:

Here, the inputs are also vectors, but the result is reduced to a single bit.

You can make an AND, OR and XOR gate.

These blocks are intended as glue logic in the Block Diagram. They are Vivado specific.

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