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Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS

Jan Cumps

Read this for info only. The project done at  the time didn't work.

I'm leaving the blog here as a testimonial that things have become easier and more streamlined with the 2.7 release of the example.

It works, and can easily be repeated, with Vitis HLS and Vivado 2020.2, on PYNQ 2.6 and 2.7.

 

There is an example project that shows how to run OpenCV functions in FPGA instead of on a processor.

This practice of off-loading heavy processing from software in the processor to hardware designs running inside the FPGA  fabric is called hardware acceleration.

I reviewed it here: Learning Xilinx Zynq: Hardware Accelerated Software.

In this post, I will try to do the same, with the 2020.2 toolchain and sources.

 

Vitis HLS is the application that you use to turn C code into VHDL or Verilog IPs.

 

earlier

I managed to compile the github version of the HelloWorld resize examples from command line, using the 2020.1 toolchain.

That was the latest chain that has been reported by users that's able to compile this example. You can see the exercise (and the changes to do in header files) in the post linked above.

I could not get the solution to compile from within the Vitis HLS IDE. But I was able to see and understand the exercise.

I'm currently trying to progress beyond the issue https://discuss.pynq.io/t/vitis-vision-core-fails-on-pynq-v2-5-1/1822.

 

I now downloaded the "2020.2 Updated" version of the Xilinx OpenCV source code, and am trying to get that compiled, then adapted to a Zynq/Pynq context.

My first attempt resulted in a corrupt Vitis HLS project. The IDE threw an unrecoverable error and core dump during the build after a while. Without details for troubleshooting.

I started over, and now have a successfult synthesis of the resize example. That's the start point of this post.

image

 

The post will be updated or adapted based on the progress.

 

Get the Xilinx Vitis Libraries and Examples

 

The Vitis libraries are a collection of hardware accelerators for Xilinx devices.

There are data compressors, encryptors, matrix solvers, …  and a hardware accelerated OpenCV API, branded Xilinx Vision.

That Vision library and its examples are what I'm interested in.

The sources are available in github, and tagged in sync with the Vitis release numbers.

I'm using Vitis and Vivado 2020.2 today, so I need to fetch that code.

This is how you get it on you development computer:

 

git clone --branch v2020.2_update1 https://github.com/Xilinx/Vitis_Libraries.git

 

The example that I'm looking for is found in the Vitis_Libraries/vision/L1/examples/resize subfolder.

 

Create a Vitis HLS project

 

This is the next step: gather the code and simulation sources, get them in a Vitis HLS project and configure it.

Start Vitis HLS 2020.2, then create a new project.

Name it Resize. Set Top Function to resize_accel.

 

image

We could define a number of settings while creating the project, but I'll do that after the creation.

So skip all but the last screen. Then set the Zynq part before confirming:

image

In my install, it doesn't know the board definition of the Pynq-Z2 that I use. I set the FPGA part by hand.

 

Configure the Vitis HLS project

 

Add source files:

The accelerator has a C++ header and source.

You add them to the project by right-clicking on the source folder in the explorer tree, then select Add Files ...

Use the L1 folder, not L2.

 

image

 

The files aren't copied in the project. They are linked to.

Then we need to set the compiler options for the source file.

I learned that the Vitis toolchain doesn't pick up includes, defines, ... that you set in the Eclipse properties. It's done differently.

Right-click on the project node and select Project Settings. Then select the Synthesis entries.

image

 

Select the .cpp file and edit the CFLAGS.

Set them to what reflects the locations for your setup.

I tried to make a Eclipse Path Variable then use the ${...} syntax, but it didn't take.

So here you go - edit to your environment:

-ID:/users/jancu/git_xilinx/Vitis_Libraries/vision/L1/include -ID:/users/jancu/git_xilinx/Vitis_Libraries/vision/L1/examples/resize -ID:/users/jancu/git_xilinx/Vitis_Libraries/vision/L1/tests/resize/resize_DOWN_BILINEAR_NO_RGB -D__SDSVHLS__ -std=c++0x

The nice thing is that this is reflected in the Eclipse Includes Indexer.

 

switch to AXI Lite instead of AXI Master interface

I noticed when using the interface in a Vivado flow, that it would use AXI Master interfaces.

I switched them into AXI light ones, like the original example I'm trying to follow.

Later I may revert this.

 

In the CPP file, the input and output declaration becomes:

    #pragma HLS INTERFACE axis    port=img_inp  // offset=slave bundle=gmem1 depth=__XF_DEPTH

    #pragma HLS INTERFACE axis    port=img_out  // offset=slave bundle=gmem2 depth=__XF_DEPTH_OUT

 

 

 

 

Add the simulation files:

Almost the same procedure, but the Test Bench node when adding the file.

Use the L1 folder, not L2.

image

 

Then go to the Project Settings again. Select the test bench source file.

Now set both CFLAGS and CSYMSFLAGS:

 

image

 

CFLAGS:

-D__SDSVHLS__ -I../vitis_lib/vision/L1/include -I../vitis_lib/vision/L1/examples/resize -I../vitis_lib/vision/L1/tests/resize/resize_DOWN_BILINEAR_NO_RGB -std=c++0x -Wno-unknown-pragmas

 

CSYMSFLAGS:

-Wno-unknown-pragmas

 

Try a Synthesis

 

This is a good time to try and build the project.

The result should be a VHDL IP that can be used in Vivado.

 

Click on the green arrow to run the synthesis. Watch the console for errors.

image

 

In the end you get a synthesis report that assesses the amount of FPGA resources will be used.

image

 

I'll try and integrate this in a Vivado block design now. For that, I first need to:

 

Export the IP as a Vivado RTL

 

Vitis HLS generates a Vivado IP when you select the Solution -> Export to RTL button.

Keep the defaults - set the language to your selection of choice.

image

 

That's it for now. We're finished in Vitis HLS.

 

 

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