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  • Author Author: Jan Cumps
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Add Pynq-Z2 board to Vivado

Jan Cumps

Instructions on how to add the Pynq-Z2Pynq-Z2 board to Vivado.

This allows you to create projects and custom FPGA bit streams for it.

 

image

image source: customer action video after completing the instruction video of Cathal McCabe listed at the end of this post.

 

In the Vivado project creation wizard, there is a possibility to prime your design from a board definition.

You don't need to find out what the exact FPGA is, and what hardware is available.

There are more project preparation tools. Constraint files and TCL files that fully define the board with all possibilities enabled.

This post focuses on the board definition.

image

 

Get the board file

 

The files listed on pync.io are not available. I found them here.

image

 

Install and register the board in Vivado

 

Then there are two options.

I used the 2nd option. You have to restart the editor.

 

The result is that you can now create projects that have the right FPGA info for the Pynq-Z2:

image

 

My goal for this week is to replicate this exercise from Cathal McCabe from the Pynq community:

 

I attached the project to this post, and the jupyter notebook.

I changed some things:

32 bit GPIO instead of 64

A reset input for the Johnson Counter module

Translated the Verilog Counter code to VHDL.

 

 

Pynq - Zync - Vivado series
Add Pynq-Z2 board to Vivado
Learning Xilinx Zynq: port a Spartan 6 PWM example to Pynq
Learning Xilinx Zynq: use AXI with a VHDL example in Pynq
VHDL PWM generator with dead time: the design
Learning Xilinx Zynq: use AXI and MMIO with a VHDL example in Pynq
Learning Xilinx Zynq: port Rotary Decoder from Spartan 6 to Vivado and PYNQ
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control
Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ
Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations
Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency
Learning Xilinx Zynq: Hardware Accelerated Software
Automate Repeatable Steps in Vivado
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design
Learning Xilinx Zynq: Logic Gates in Vivado
Learning Xilinx Zynq: Interrupt ARM from FPGA fabric
Learning Xilinx Zynq: reuse and combine components to build a multiplexer
PYNQ version 2.7 (Austin) is released
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors
Use the ZYNQ XADC with DMA part 1: bare metal
Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse
Attachments:
johnson_counter.zip
johnson_counter_jupyter_notebook.zip
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