The Art of FPGA Design Season 2 - Digital Signal Processing, from Algorithm to FPGA Bitstream

Hi,

This is season 2 of the Art of FPGA Design blog. I plan to add a new post every Tuesday but depending on how long it will take me to create the content some posts could appear every other week. I have outlined below the first few posts I am planning to make so you can have an idea on what to expect, As I create the content, they will turn into links to actual posts.

This is a change of direction from the first season of The Art of FPGA Design blog. While not a prerequisite for following along with this second season, reading it cannot hurt either.

I will turn my focus on Digital Signal Processing using FPGAs this time. However, this is neither a DSP gentle introduction, nor a primer on FPGA design. There are numerous good resources available for both subjects, including many free ones and there is no need to reinvent the wheel. So at least some level of familiarity with both areas is expected. If this feels to you like a dive into the deep end on either subject please comment and I will try to compile a list of resources that could be used to quickly get up to speed. If you think you can suggest something please comment and I will add the links to this blog post.

What this blog will try to address instead is how to cross the gap between a DSP algorithm and its efficient implementation in an FPGA, something that is rarely explained or even discussed. How do you go from an algorithm specification, which is essentially mathematics to an actual hardware implementation, where you have to live within the constraints imposed on you by the laws of physics. Normally, in a larger organization the two roles are filled by two different persons, a DSP System Architect and a Hardware Designer. They are highly specialized roles, requiring two different skills sets and using different design tools. Even if the same person is wearing both hats, the question still remains, how do you bridge the chasm between mathematics and physics?

If you happen to find yourself on either side of that precipice wondering how are you going to get to the other side, I invite you to accompany me on this trip.

Full disclosure:

While I do work for Xilinx, this is my personal blog. The ideas expressed here are my own and do not represent the views or opinions of my employer. Although I will talk about Xilinx FPGAs among other things, this is not a hidden marketing promotional campaign - this is a technical blog about the Art of FPGA Design.

The algorithms and code examples that will be used here are placed in the public domain and can be freely used by anybody without any restrictions, although providing attribution would be nice. On the other hand they come with no warranty of any kind, they are provided "as is" and you use them at your own risk.

The Art of FPGA Design Season 2 Post 1 - Crossing the gap between mathematics and physics

The Art of FPGA Design Season 2 Post 2 - The basic building blocks on the DSP algorithm side

The Art of FPGA Design Season 2 Post 3 - The basic building blocks on the FPGA implementation side

The Art of FPGA Design Season 2 Post 4 - Register pushing and the pipeline cut

The Art of FPGA Design Season 2 Post 5 - The Single Rate non-symmetric FIR, direct and transpose architectures

The Art of FPGA Design Season 2 Post 6 - The Single Rate even-symmetric FIR

The Art of FPGA Design Season 2 Post 7  - The Single Rate odd-symmetric FIR

The Art of FPGA Design Season 2 Post 8 - The Single Rate symmetric FIR, low latency transposed architecture

The Art of FPGA Design Season 2 Post 9 - The Single Rate Half-Band FIR

The Art of FPGA Design Season 2 Post 10 - The Single Rate Half-Band FIR Interpolator

The Art of FPGA Design Season 2 Post 11 - The Single Rate Half-Band FIR Decimator

The Art of FPGA Design Season 2 Post 12 - Polyphase FIRs

The Art of FPGA Design Season 2 Post 13 - Polyphase Interpolators

The Art of FPGA Design Season 2 Post 14 - Polyphase Decimators

The Art of FPGA Design Season 2 Post 15 - Taking advantage of coefficient symmetry in Polyphase FIRs

The Art of FPGA Design Season 2 Post 16 - Multichannel and Overclocking FIRs - The Single Rate Non-Symmetric Case

The Art of FPGA Design Season 2 Post 17 - Multichannel and Overclocking FIRs - The Single Rate Symmetric Case

The Art of FPGA Design Season 2 Post 18 - Multichannel Symmetric FIRs

and so on, I plan to do at least 40 posts showing how to turn various DSP Algorithms into efficient hardware implementations.

Previously on the Art of FPGA Design:

The Art of FPGA Design Season 1 - A 36-post blog on advanced VHDL design topics for Xilinx FPGAs