Next I'm going to have a quick look at the stability of the original circuit.

Remembering back to the things I learnt many years ago [I wasn't a very diligent student and didn't pay as much attention as I should have done], the

necessary conditions for sustained oscillation in a circuit are that there should be feedback and, at some frequency,

there should be gain of more than one (otherwise any oscillation will just die away) AND the signal fed back should

reinforce and not counter the oscillation. Stability is more than just the absence of oscillation of course, but it's

a good starting point and the tools that we use to look at it will give us some idea of how the circuit will behave

generally (whether it will overshoot and ring if hit by a fast edge for instance). All of this was investigated by

people back in the 1940s, the two most well known being Nyquist and Bode. Bode's method, derived from that of

Nyquist, used separate gain and phase plots and was also useful where systems were measured (rather than the curves

being pieced together from knowledge of how the individual circuit elements would behave theoretically). I'm going to

try and see if I can get some Bode plots for this circuit using the simulator and then look at the effect that having

some inductance in the test leads, used to connect the load to the circuit under test, might have. I haven't got a

clue how you SHOULD do this [I was never taught anything about simulation], but other people do it so it can't be too

difficult. [Just don't assume I know what I'm doing, that's all.]

Here's the circuit I'm using:

What I'm doing is simply breaking the loop, feeding a signal in from a signal generator and recording the signal that

finds its way all around the loop and back to the break point. I'm measuring the open-loop response rather than the

closed-loop response. I've set the normal circuit input to a fixed value of 2V. By the way, that break in the loop

can occur anywhere around the loop. That seems a bit odd at first but, if you think about it, wherever it is that you

break the loop, one complete circuit round has to have the same effect. The break must be in the actual loop, though,

whether it's in the forward path or the fed back path.

There's a complication with this circuit, though. The feedback sets the operating point for the MOSFET. With the loop

broken, it won't find the correct operating point and I'll probably just be sending a small signal round the loop

through the gate-source capacitance and the results will be wrong because I'll be measuring something different to

what the real circuit does. So, what I did was to get the simulator to analyse the dc nodal voltages with the loop

intact, read the voltage at the end of the diode where I'm going to attach the signal generator, and then I added

that voltage as a dc offset to the signal generator so that the small sinewave it uses to do the frequency analysis

was swinging around that operating point. [I imagine that there's some clever way to get the simulator to do that for

itself, if only I knew what it was - I couldn't think of anything that wouldn't upset the results.]

Here are the plots of gain and phase for the circuit with no added inductance on the output.

We can derive two figures from these plots that give us some measure of how far we are from oscillation. The phase

margin is how close the phase gets to zero degrees (or +-360, depending how the simulator likes to give it to us on

the plot) before the gain gets down to unity (0dB). The gain margin is how far the gain is below 0dB when the phase

gets to zero degrees. People sometimes define the phase margin as being the value when we get to unity gain. I think

that comes from considering the simpler situation of amplifiers where the gain and phase will often both decline

nicely at higher frequencies and the worst case for the phase is then the same point as the gain falling to unity.

With something like this, where the output load has a major effect on how the loop performs (the output load isn't

inside the loop, but the current through it also flows through the current sense resistor which is), we're rapidly

moving away from a simple textbook example.

I've drawn these onto the plots with a paint package. The phase margin is 90 degrees and the gain margin is 34dB.

They are both very safe. People seem to have different ideas about what constitutes an adequate gain and phase

margin. Integrated Electronics (Millman and Halkias, 1972) says 'a linear amplifier of good stability requires gain

and phase margins of at least 10dB and 50 degrees respectively'. Other books I've read suggest 30 degrees is

sufficient for control systems. The complication is that we are just looking here at one aspect of how the control

loop behaves and there are other criteria to look at too. For instance, we may want to trade some stability for

better agility and a faster response (one immediate observation we can make of the gain plot is that the loop runs

out of gain at 23kHz - that means there's no possibility of oscillation further up, but the load isn't going to be

doing very much either).

Here is the same test again, but this time with two test leads each having 1.4uH of inductance. (That's one metre of

1.6mm [14 AWG] diameter wire with no coupling between the leads - in practice there would be some mutual coupling

where the leads come together at the load and at the circuit being tested, even if you spaced them as far apart as

possible in between.)

This time the phase margin is just 23 degrees and the gain margin is 13dB. Although it's still stable [in the sense

of not oscillating], the much lower phase margin means that it may overshoot and ring on a fast edge. [What would be

interesting here would be for me to try a range of different inductances to get a feel for how the two plots vary.

I'll have a go at that over the weekend if I've got time.]

Remember that this is the result of a simulator running, so it's only as good as the models and I wouldn't expect it

to be totally accurate, particularly as the frequency goes up and parasitic capacitances come into play. In any case

the models will be using typical figures (or perhaps worst case 25C figures for the leakages and bias currents?) so

there will be more variation there. Also, I substituted an alternative part for the MOSFET that Peter originally had

and the internal capacitances between the terminals will be different. So this is all a bit rough and ready - it

helps us understand and is a guide to what the circuit would do but it isn't reality. The other point to remember is

that this is the small-signal performance - things will be different for large signals where op-amp slew rate comes

into play and there is also the possibility that signals will distort.

Edited 12th June 2017: I pasted in the wrong circuit and curves for the case with lead inductance (I had the 1mH ones,

and they should have been the 1.4uH ones) - I've just replaced them.

Next I'm going to have a quick look at the stability of the original circuit.

Remembering back to the things I learnt many years ago [I wasn't a very diligent student and didn't pay as much attention as I should have done], the

necessary conditions for sustained oscillation in a circuit are that there should be feedback and, at some frequency,

there should be gain of more than one (otherwise any oscillation will just die away) AND the signal fed back should

reinforce and not counter the oscillation. Stability is more than just the absence of oscillation of course, but it's

a good starting point and the tools that we use to look at it will give us some idea of how the circuit will behave

generally (whether it will overshoot and ring if hit by a fast edge for instance). All of this was investigated by

people back in the 1940s, the two most well known being Nyquist and Bode. Bode's method, derived from that of

Nyquist, used separate gain and phase plots and was also useful where systems were measured (rather than the curves

being pieced together from knowledge of how the individual circuit elements would behave theoretically). I'm going to

try and see if I can get some Bode plots for this circuit using the simulator and then look at the effect that having

some inductance in the test leads, used to connect the load to the circuit under test, might have. I haven't got a

clue how you SHOULD do this [I was never taught anything about simulation], but other people do it so it can't be too

difficult. [Just don't assume I know what I'm doing, that's all.]

Here's the circuit I'm using:

What I'm doing is simply breaking the loop, feeding a signal in from a signal generator and recording the signal that

finds its way all around the loop and back to the break point. I'm measuring the open-loop response rather than the

closed-loop response. I've set the normal circuit input to a fixed value of 2V. By the way, that break in the loop

can occur anywhere around the loop. That seems a bit odd at first but, if you think about it, wherever it is that you

break the loop, one complete circuit round has to have the same effect. The break must be in the actual loop, though,

whether it's in the forward path or the fed back path.

There's a complication with this circuit, though. The feedback sets the operating point for the MOSFET. With the loop

broken, it won't find the correct operating point and I'll probably just be sending a small signal round the loop

through the gate-source capacitance and the results will be wrong because I'll be measuring something different to

what the real circuit does. So, what I did was to get the simulator to analyse the dc nodal voltages with the loop

intact, read the voltage at the end of the diode where I'm going to attach the signal generator, and then I added

that voltage as a dc offset to the signal generator so that the small sinewave it uses to do the frequency analysis

was swinging around that operating point. [I imagine that there's some clever way to get the simulator to do that for

itself, if only I knew what it was - I couldn't think of anything that wouldn't upset the results.]

Here are the plots of gain and phase for the circuit with no added inductance on the output.

We can derive two figures from these plots that give us some measure of how far we are from oscillation. The phase

margin is how close the phase gets to zero degrees (or +-360, depending how the simulator likes to give it to us on

the plot) before the gain gets down to unity (0dB). The gain margin is how far the gain is below 0dB when the phase

gets to zero degrees. People sometimes define the phase margin as being the value when we get to unity gain. I think

that comes from considering the simpler situation of amplifiers where the gain and phase will often both decline

nicely at higher frequencies and the worst case for the phase is then the same point as the gain falling to unity.

With something like this, where the output load has a major effect on how the loop performs (the output load isn't

inside the loop, but the current through it also flows through the current sense resistor which is), we're rapidly

moving away from a simple textbook example.

I've drawn these onto the plots with a paint package. The phase margin is 90 degrees and the gain margin is 34dB.

They are both very safe. People seem to have different ideas about what constitutes an adequate gain and phase

margin. Integrated Electronics (Millman and Halkias, 1972) says 'a linear amplifier of good stability requires gain

and phase margins of at least 10dB and 50 degrees respectively'. Other books I've read suggest 30 degrees is

sufficient for control systems. The complication is that we are just looking here at one aspect of how the control

loop behaves and there are other criteria to look at too. For instance, we may want to trade some stability for

better agility and a faster response (one immediate observation we can make of the gain plot is that the loop runs

out of gain at 23kHz - that means there's no possibility of oscillation further up, but the load isn't going to be

doing very much either).

Here is the same test again, but this time with two test leads each having 1.4uH of inductance. (That's one metre of

1.6mm [14 AWG] diameter wire with no coupling between the leads - in practice there would be some mutual coupling

where the leads come together at the load and at the circuit being tested, even if you spaced them as far apart as

possible in between.)

This time the phase margin is just 23 degrees and the gain margin is 13dB. Although it's still stable [in the sense

of not oscillating], the much lower phase margin means that it may overshoot and ring on a fast edge. [What would be

interesting here would be for me to try a range of different inductances to get a feel for how the two plots vary.

I'll have a go at that over the weekend if I've got time.]

Remember that this is the result of a simulator running, so it's only as good as the models and I wouldn't expect it

to be totally accurate, particularly as the frequency goes up and parasitic capacitances come into play. In any case

the models will be using typical figures (or perhaps worst case 25C figures for the leakages and bias currents?) so

there will be more variation there. Also, I substituted an alternative part for the MOSFET that Peter originally had

and the internal capacitances between the terminals will be different. So this is all a bit rough and ready - it

helps us understand and is a guide to what the circuit would do but it isn't reality. The other point to remember is

that this is the small-signal performance - things will be different for large signals where op-amp slew rate comes

into play and there is also the possibility that signals will distort.

Edited 12th June 2017: I pasted in the wrong circuit and curves for the case with lead inductance (I had the 1mH ones,

and they should have been the 1.4uH ones) - I've just replaced them.